MAX3885ECB-TD Maxim Integrated, MAX3885ECB-TD Datasheet - Page 5

• Manufacturer Part Number: MAX3885ECB-TD
• Description: Serializers & Deserializers - Serdes 3.3V 2.488Gbps SDH/ SONET 1
• Manufacturer: Maxim Integrated

Specifications of MAX3885ECB-TD

• Data Rate: 2.488 Gbps, 155 Mbps
• Number Of Inputs: 1
• Number Of Outputs: 16
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 200 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

The MAX3885 deserializer uses a 16-bit shift register,
16-bit parallel output register, 4-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
Figure 2. Functional Diagram
Figure 3. Timing Diagram
SYNC+
SCLK+
SYNC-
SCLK-
SD+
SD-
D15
TRANSMITTED FIRST
100Ω
PECL
PECL
D14
LVDS
D13
(MSB)
(LSB) PD0
_______________________________________________________________________________________
SYNC
SCLK
PCLK
PD15
PD1
MAX3885
SD
REGISTER
•
•
•
16-BIT
Detailed Description
SHIFT
COUNTER
4-BIT
1:16 Deserializer with LVDS Outputs
D15
PARALLEL
REGISTER
D0
D1
OUTPUT
16-BIT
LVDS
LVDS
LVDS
LVDS
+3.3V, 2.488Gbps, SDH/SONET
D16
D17
D31
PD15+
PD15-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential
D32
D33
D47
Low-Voltage Differential-Signal (LVDS)
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D48
D49
D64
Inputs and Outputs
D66
D65
D80
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