MAX3891ECB-TD Maxim Integrated, MAX3891ECB-TD Datasheet - Page 6
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MAX3891ECB-TD
Manufacturer Part Number
MAX3891ECB-TD
Description
Serializers & Deserializers - Serdes
Manufacturer
Maxim Integrated
Type
Serializerr
Datasheet
1.MAX3891ECBD.pdf
(12 pages)
Specifications of MAX3891ECB-TD
Data Rate
2.5 Gbit/s
Input Type
LVPECL
Output Type
LVPECL
Number Of Inputs
16
Number Of Outputs
1
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TQFP-64 EP
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
The setup and hold-time specifications assume that the
parallel clock-input signal (PCLKI) and parallel-data
input signal (PDI_) are from the same source. They
should have identical common-mode voltages, signal
amplitudes, and slew rates. If PCLKI and PDI_ differ
significantly, the setup and hold-time requirements
must be modified to account for these differences.
Define t
time requirement when there are significant differences
between PCLKI and PDI_.
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET,
with Clock Synthesis and LVPECL Inputs
Figure 2. Functional Block Diagram
6
_______________________________________________________________________________________
PCLKI+
PCLKI-
RCLK+
RCLK-
PDI15
DEG
PDI1
PDI0
Setup and Hold Time Requirements
as the adjustment to the setup and hold-
Applications Information
PECL
PECL
PECL
PECL
PECL
BUF
PHASE/FREQ
DETECT
PARALLEL
REGISTER
16-BIT
INPUT
FIL+ FIL- CLKSET
FILTER
PRESCALER
VCO
where t
lel-data and clock-input signals, V
input high and low voltage, respectively, of the parallel-
data and clock-input signals, and VCM
ence in common-mode voltages of the parallel-data
and clock-input signals.
PCLKO+ PCLKO-
DIVIDE
BY 16
PECL
T
is the transition time (20%–80%) of the paral-
t
DEG
=
VCM
LATCH
SHIFT
PARALLEL
REGISTER
DIFF
16-BIT
SHIFT
×
MAX3891
V
OH
0 6 .
PECL
PECL
t
CML
T
-
OH
V
OL
and V
DIFF
SCLKO+
SCLKO-
SOS
SLBO+
SLBO-
SDO+
SDO-
is the differ-
OL
are the