MAX3301EETJ Maxim Integrated, MAX3301EETJ Datasheet - Page 19

• Manufacturer Part Number: MAX3301EETJ
• Description: USB Interface IC
• Manufacturer: Maxim Integrated

Specifications of MAX3301EETJ

• Operating Supply Voltage: 3 V to 4.5 V
• Operating Supply Current: 5 uA

USB On-the-Go Transceivers and Charge Pumps
Figure 18. Write Byte Format
Both SCL and SDA assert high when the interface is not
busy. A master device signals the beginning of a trans-
mission with a start (S) condition by transitioning SDA
from high to low while SCL is high. The master issues a
stop (P) condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another trans-
mission (see Figure 14).
One data bit is transferred during each clock pulse. The
data on SDA must remain stable while SCL is high (see
Figure 16).
The acknowledge bit (ACK) is the 9th bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX3301E/MAX3302E generate
Figure 16. Bit Transfer
Figure 17. Acknowledge
TRANSMITTER
SDA
SCL
RECEIVER
S
SDA BY
SDA BY
SCL
A6
CONDITION
DATA LINE STABLE,
START
S
A5
DATA VALID
SLAVE ADDRESS
A4
(7 BITS)
______________________________________________________________________________________
CLOCK PULSE FOR ACKNOWLEDGEMENT
A3
1
CHANGE OF DATA
A2
ALLOWED
A1
Start and Stop Conditions
2
A0
R/W
0
8
A
Acknowledge
MSB
Bit Transfer
9
REGISTER ADDRESS
(8 BITS)
an ACK when receiving an address or data by pulling
SDA low during the ninth clock period. When transmit-
ting data, the MAX3301E/MAX3302E wait for the receiv-
ing device to generate an ACK. Monitoring ACK allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is busy
or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master should reat-
tempt communication at a later time.
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address (see Figure 15). When idle, the
MAX3301E/MAX3302E wait for a START condition fol-
lowed by its slave address. The LSB of the address
word is the read/write (R/W) bit. R/W indicates whether
the master is writing to or reading from the
MAX3301E/MAX3302E (R/W = 0 selects the write con-
dition, R/W = 1 selects the read condition). After
receiving the proper address, the MAX3301E/
MAX3302E issue an ACK.
The MAX3301E/MAX3302E have two possible addresses
(see Table 5). Address bits A6 through A1 are preset,
while a reset condition or an I
loads the value of A0 from ADD. Connect ADD to GND to
set A0 to 0. Connect ADD to V
up to two MAX3301E’s or two MAX3302E’s to share the
same bus.
Writing data to the MAX3301E/MAX3302E requires the
transmission of at least 3 bytes. The first byte consists of
the MAX3301E/MAX3302E’s 7-bit slave address, fol-
lowed by a 0 (R/W bit). The second byte determines
which register is to be written to. The third byte is the
new data for the selected register. Subsequent bytes
are data for sequential registers. Figure 18 shows the
typical write byte format.
Reading data from the MAX3301E/MAX3302E requires
the transmission of at least 3 bytes. The first byte con-
sists of the MAX3301E/MAX3302E’s slave address, fol-
lowed by a 0 (R/W bit). The second byte selects the
register from which data is read. The third byte consists
LSB
A
MSB
L
(8 BITS)
DATA
to set A0 to 1. This allows
2
C general call address
Write Byte Format
Read Byte Format
Slave Address
LSB
A
P
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