MAX3107EVKIT+ Maxim Integrated, MAX3107EVKIT+ Datasheet - Page 27

• Manufacturer Part Number: MAX3107EVKIT+
• Description: UART Interface IC UART with integrated Oscillator
• Manufacturer: Maxim Integrated

Specifications of MAX3107EVKIT+

• Number Of Channels: 1
• Data Rate: 24 Mbps
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V
• Supply Current: 4 mA

Maxim Integrated
LSR—Line Status Register
The LSR shows all errors related to the word previously read out of the RxFIFO. The LSR bits are not cleared upon a
read; these bits stay set until the character with errors is read out of the RHR. The LSR also reflects the current state
of the CTS input.
Bit 7: CTSbit
The CTSbit reflects the current logic state of the CTS input. This bit is cleared when the CTS input is low. Following a
power-up or reset, the logic state of the CTS bit depends on the CTS input.
Bit 6: No Function
Bit 5: RxNoise
If noise is detected on the RX input during reception of a character, the RxNoise bit is set for that character. The
RxNoise bit indicates that there was noise on the line while the character most recently read from the RHR was
received. The RxNoise flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[5].
Bit 4: RxBreak
If a line BREAK (RX input low for a period longer than the programmed character duration) is detected, a BREAK
character is put in the RxFIFO and the RxBreak bit is set for this character. A BREAK character is represented by an
all-zeros data character. The RxBreak bit distinguishes a regular character with all zeros from a BREAK character.
LSR[4] corresponds to the character most recently read from the RHR. The RxBreak flag can generate an ISR[0] inter-
rupt, if enabled through LSRIntEn[4].
Bit 3: FrameErr
The FrameErr bit is set high when the received data frame does not match the expected frame format in length.
FrameErr corresponds to the frame error of the character most recently read from the RHR. A frame error is related to
errors in expected STOP bits.
The FrameErr flag can generate an ISR[0] interrupt, if enabled, through LSRIntEn[3].
Bit 2: RxParityErr
If the parity computed on the character being received does not match the received character’s parity bit, the
RxParityErr bit is set for that character. RxParityErr indicates a parity error for the word most recently read from the RHR.
In 9-bit multidrop mode (MODE2[6] = 1) the receiver does not check parity and the RxParityErr represents the 9th (i.e.,
address or data) bit.
The RxParityErr flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[2].
Bit 1: RxOverrun
If the receive FIFO is full and additional data is received that does not fit into the receive FIFO, the RxOverrun bit is set.
The receive FIFO retains the data in it and discards all new data that does not fit into it. The RxOverrun indication is
cleared after the LSR is read or the RxFIFO level falls below its maximum. The RxOverrun flag can generate an ISR[0]
interrupt, if enabled through LSRIntEn[1].
ADDRESS:
MODE:
RESET
NAME
BIT
CTSbit
X
7
0x04
R
SPI/I
—
6
0
RxNoise
2
5
0
C UART with 128-Word FIFOs
RxBreak
4
0
FrameErr
3
0
RxParityErr
2
0
MAX3107
RxOverrun
1
0
RTimeout
0
0
27