MAX7469UTP Maxim Integrated, MAX7469UTP Datasheet - Page 11

• Manufacturer Part Number: MAX7469UTP
• Description: Video ICs
• Manufacturer: Maxim Integrated

Successful data transfers are acknowledged with an
acknowledge bit (ACK) or a not-acknowledge bit
(NACK). Both the master and the MAX7469/MAX7470
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period
of the clock pulse (Figure 4). To generate a NACK, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and leaves it high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccess-
ful data transfer happens if a receiving device is busy or
if a system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
The MAX7469/MAX7470 generate an acknowledge bit
when receiving an address or data by pulling SDA low
during the ninth clock pulse. When transmitting data
during a read, the MAX7469/MAX7470 do not drive
SDA during the ninth clock pulse (i.e., the external
pullups define the bus as a logic-high) so that the
receiver of the data can pull SDA low to acknowledge
receipt of data.
Figure 4. Acknowledge and Not-Acknowledge Bits
Figure 5. Slave-Address Byte Definition
.
SDA
SCL
Acknowledge Bit (ACK) and Not-Acknowledge Bit
MSB
1
SDA
SCL
______________________________________________________________________________________
0
S
0
1
1
HDTV Continuously Variable
(NACK)
0
A bus master initiates communication with a slave device
by issuing a START condition, followed by the 7-bit slave
address (Figure 5). When idle, the MAX7469/MAX7470
wait for a START condition, followed by their slave
address. The serial interface compares each address bit
by bit, allowing the interface to power down and discon-
nect from SCL immediately if an incorrect address is
detected. After recognizing a START condition followed
by the correct address, the MAX7469/MAX7470 are
ready to accept or send data. The least significant bit
(LSB) of the address byte (R/W) determines whether the
master is writing to or reading from the MAX7469/
MAX7470 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the proper
address, the MAX7469/MAX7470 (slave) issue an ACK
by pulling SDA low for one clock cycle.
The MAX7469/MAX7470 slave address consists of 5
fixed bits, A6–A2 (set to 10010), followed by 2 pin-pro-
grammable bits, A1 and A0. The most significant
address bit (A6) is transmitted first, followed by the
remaining bits. Addresses A1 and A0 can also be driven
dynamically if required, but the values must be stable
when they are expected in the address sequence.
Anti-Aliasing Filters
A1
NOT ACKNOWLEDGE
ACKNOWLEDGE
8
LSB
A0
9
R/W
Slave Address
ACK
11