MAX7300AAI-T Maxim Integrated, MAX7300AAI-T Datasheet - Page 7

• Manufacturer Part Number: MAX7300AAI-T
• Description: Interface - I/O Expanders 2.5-5.5V 20/28 Port I/O Expander
• Manufacturer: Maxim Integrated
• Series: MAX7300r

Specifications of MAX7300AAI-T

• Operating Supply Voltage: 2.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Output Current: 10 mA
• Power Dissipation: 727 mW

The MAX7300 operates as a slave that sends and
receives data through an I
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7300, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7300 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7300 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7300
7-bit slave address plus R/ W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
Table 1. Port Configuration Map
Table 2. Port Configuration Matrix
Port Configuration for P7, P6, P5, P4
Port Configuration for P11, P10, P9, P8
Port Configuration for P15, P14, P13, P12
Port Configuration for P19, P18, P17, P16
Port Configuration for P23, P22, P21, P20
Port Configuration for P27, P26, P25, P24
Port Configuration for P31, P30, P29, P28
Output
MODE
Input
Input
GPIO Input with Pullup
without Pullup
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
GPIO Output
FUNCTION
GPIO Input
REGISTER
_______________________________________________________________________________________
DO NOT USE THIS SETTING
2
C-compatible 2-wire inter-
Serial Interface
Serial Addressing
input logic level
Register bit = 0
Register bit = 1
Register bit =
(0x20–0x5F)
REGISTER
PORT
CODE (HEX)
ADDRESS
0x0A
0x0B
0x0C
0x0D
0x09
0x0E
0x0F
Active-low logic output
Active-high logic output
Schmitt logic input
Schmitt logic input with pullup
PIN BEHAVIOR
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
The acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7300, the
MAX7300 generates the acknowledge bit since the
D7
28-Port I/O Expander
P11
P15
P19
P23
P27
P31
P7
D6
D5
START and STOP Conditions
P10
P14
P18
P22
P26
P30
REGISTER DATA
P6
CODE (HEX)
0x09 to 0x0F
0x09 to 0x0F
0x09 to 0x0F
0x09 to 0x0F
ADDRESS
D4
D3
P13
P17
P21
P25
P29
P5
P9
UPPER
CONFIGURATION
D2
Acknowledge
0
0
1
1
Bit Transfer
BIT PAIR
PORT
D1
LOWER
P12
P16
P20
P24
P28
P4
P8
0
1
0
1
D0
7