MAX7310AUE Maxim Integrated, MAX7310AUE Datasheet - Page 6

• Manufacturer Part Number: MAX7310AUE
• Description: Interface - I/O Expanders
• Manufacturer: Maxim Integrated
• Series: MAX7310r

Specifications of MAX7310AUE

• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16
• Output Current: 30 mA

Table 1 is the register address table. Tables 2–6 list
register 0 through register 4 information.
The MAX7310 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX7310, and generates the SCL clock that synchro-
nizes the data transfer (Figure 2).
Each transmission consists of a start condition sent by
a master, followed by the MAX7310 7-bit slave address
plus an R/W bit, a register address byte, one or more
data bytes, and finally a stop condition (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a start (S) condition by transitioning SDA from
high to low while SCL is high. When the master has fin-
ished communicating with the slave, it issues a stop (P)
condition by transitioning SDA from low to high while
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Figure 2. 2-Wire Serial Interface Timing Diagrams
Figure 3. Start and Stop Conditions
6
_______________________________________________________________________________________
SDA
SCL
t
HD, STA
START CONDITION
t
LOW
SDA
SCL
Start and Stop Conditions
t
R
CONDITION
START
t
HIGH
S
t
Serial Interface
SU, DAT
Serial Addressing
t
F
t
HD, DAT
t
SU, STA
REPEATED START CONDITION
SCL is high. The bus is then free for another transmis-
sion (Figure 3).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7310, the
MAX7310 generates the acknowledge bit since the
MAX7310 is the recipient. When the MAX7310 is trans-
mitting to the master, the master generates the
acknowledge bit.
The MAX7310 has a 7-bit-long slave address (Figure
6). The 8th bit following the 7-bit slave address is the
R/W bit. Set this bit low for a write command and high
for a read command.
t
HD, STA
CONDITION
STOP
P
t
SU, STO
STOP CONDITION
Slave Address
Acknowledge
t
BUF
Bit Transfer
START CONDITION