CAT9554AWI-G Catalyst (ON Semiconductor), CAT9554AWI-G Datasheet
CAT9554AWI-G
Specifications of CAT9554AWI-G
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CAT9554AWI-G Summary of contents
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CAT9554, CAT9554A 2 8-bit I C and SMBus I/O Port with Interrupt Description The CAT9554 and CAT9554A are CMOS devices that provide 8−bit parallel input/output port expansion for I applications. These I/O expanders provide a simple solution in applications where ...
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SCL INPUT FILTER SDA POWER− RESET V SS Table 1. PIN DESCRIPTION SOIC / TSSOP TQFN 4−7 2− 9−12 7− ...
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Table 4. D.C. OPERATING CHARACTERISTICS Symbol Parameter SUPPLIES V Supply voltage CC I Supply current CC I Standby current stbl I Standby current stbh V Power−on reset voltage POR SCL, SDA, INT V (Note 4) Low level input voltage IL ...
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Table 5. A.C. CHARACTERISTICS Symbol F Clock Frequency SCL t START Condition Hold Time HD:STA t Low Period of SCL Clock LOW t High Period of SCL Clock HIGH t START Condition Setup Time SU:STA t Data In Hold Time ...
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F SCL t SU:STA t HD:STA SDA IN SDA OUT Pin Description SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull−up resistor ...
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INT: Interrupt Output The open−drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input returns to its ...
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Functional Description The CAT9554 and CAT9554A general purpose input/ output (GPIO) peripherals provide up to eight I/O ports, 2 controlled through compatible serial interface. The CAT9554/9554A support the I 2 transmission protocol. This I C Bus protocol ...
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Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line ...
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The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register ...
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Power−On Reset Operation When the power supply is applied to V power−on reset pulse holds the CAT9554/9554A in a reset state until V reaches V level. At this point, the reset CC POR slave address R ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC−16, 150 mils CASE 751BG−01 ISSUE O SYMBOL ...
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D PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A3 0.20 REF b 0.25 0.30 D 3.90 4.00 D2 2.00 −−− E 3.90 4.00 E2 2.00 −−− e 0.65 BSC L 0.45 −−− Notes: ...
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PIN#1 IDENTIFICATION TOP VIEW D SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP16, 4.4x5 CASE 948AN−01 ISSUE O SYMBOL MIN A A1 0.05 A2 0.85 b ...
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... SOIC CAT9554YI−G TSSOP CAT9554YI−GT2 TSSOP CAT9554HV4I−G TQFN CAT9554HV4I−GT2 TQFN CAT9554AWI−G SOIC CAT9554AWI−GT2 SOIC CAT9554AYI−G TSSOP CAT9554AYI−GT2 TSSOP CAT9554AHV4I−G TQFN CAT9554AHV4I−GT2 TQFN 10. All packages are RoHS−compliant (Lead−free, Halogen−free). 11. The standard lead finish is NiPdAu. ...