SAP51C-A-G1-R ZMDI, SAP51C-A-G1-R Datasheet - Page 26

• Manufacturer Part Number: SAP51C-A-G1-R
• Description: Interface - Specialized ASI
• Manufacturer: ZMDI

Specifications of SAP51C-A-G1-R

• Rohs: yes
• Product Type: Actuator Sensor Interface IC
• Operating Supply Voltage: 16 V to 34 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-20
• Minimum Operating Temperature: - 25 C

3.3. Firmware Area Programming
In order to program one of the 5-bit cells of the Firmware Area (address 4…8) a special master call according
to Table 10 must be applied, followed by a DEXG or WPAR call immediately. Write access to the Firmware
Area is possible as long as the Lock_EE_PRG flag is not set. The write procedure is started after receipt of
the DEXG/WPAR call. Finish of write procedure may be observed at the status register S0 as described
above.
The analogue circuitry trim information (address 9…11) can be written by special test mode operation only.
There is no possibility to read out the E²PROM data directly. However, AS-i-related configuration data like
ID_Code may be read by the respective Read_ID_Code master request.
Table 10: SAP5 E²PROM - User and Firmware Area Programming
Internal
E²PROM
Address
0
1
2
3
4
5
6
7
8
9
10
11
1
2
I4=‘1’. Note: Differing from regular WPAR/DEXG calls, the slave always returns the received data bits I3…I0.
Data Sheet
October 20, 2011
according to Table 7
according to Table 6 with information bits corresponding to the left-hand column; DEXG if I4=’0’, WPAR if
SAP5S / SAP51
Universal Actuator-Sensor Interface IC
User Area
E²PROM Cell Content
A4 … A0
ID1_Bit3 … ID1_Bit0
ID1_Bit3 … ID1_Bit0
Not implemented
Synchronous_Data_IO
ID_Bit3 … ID_Bit0
Inhibit_Write_ID1
ID2_Bit3 … ID2_Bit0
P1_Delay_Activation
IO_Bit3 … IO_Bit0
Lock_EE_PRG
Delay_Mode
Invert_Data_In
Inhibit_BR01
Inhibit_Watchdog
P2_Sync_Activation
Ext_Addr_4I/4O_Mode
Parallel_Out_4I/4O
Master_Mode
P0_Watchdog_Activation
Analogue circuitry trim information
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 3.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
Firmware Area
Programming Master Calls
ADRA Master Call
WID1 Master Call
I4
I3 … I0
I4
I3 … I0
I4
I3 … I0
I4
I3
I2
I1
I0
I4
I3
I2
I1
I0
Accessible by ZMDI only
Set ID Code (RDIO)
Set ID Code 2 (RID1)
Set IO Config (RDID)
Set Control Code (RID2)
Set Control Code 2 (RES)
DEXG/WPAR
DEXG/WPAR
2
2
1
1
+ DEXG/WPAR
1
+ DEXG/WPAR
+ DEXG/WPAR
1
1
+
+
26 of 63
2
2
2