XRT83L314ES Exar, XRT83L314ES Datasheet - Page 58

• Manufacturer Part Number: XRT83L314ES
• Description: LIN Transceivers
• Manufacturer: Exar

Specifications of XRT83L314ES

• Product Category: LIN Transceivers
• Rohs: yes

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
TERSEL1
TERSEL0
RxJASEL
TxJASEL
RxTSEL
TxTSEL
FIFOS
JABW
N
AME
T
ABLE
Receive Termination Select
Upon power up, the receiver is in "High" impedance. RxTSEL is
used to switch between the internal termination and "High" imped-
ance.
0 = "High" Impedance
1 = Internal Termination
Transmit Termination Select
Upon power up, the transmitter is in "High" impedance. TxTSEL is
used to switch between the internal termination and "High" imped-
ance.
0 = "High" Impedance
1 = Internal Termination
Receive Line Impedance Select
TERSEL[1:0] are used to select the line impedance for T1/J1/E1.
00 = 100
01 = 110
10 = 75
11 = 120
Receive Jitter Attenuator Select
RxJASEL is used to enable the receiver jitter attenuator.
default, RxJASEL is disabled.
0 = Disabled
1 = Enabled
Transmit Jitter Attenuator Select
TxJASEL is used to enable the transmitter jitter attenuator. By
default, TxJASEL is disabled.
0 = Disabled
1 = Enabled
Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz)
The jitter bandwidth is a global setting that is applied to both the
receiver and transmitter jitter attenuator.
0 = 10Hz
1 = 1.5Hz
FIFO Depth Select
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (within the jitter attenuator blocks). The delay of the
FIFO is equal to ½ the FIFO depth. This is a global setting that is
applied to both the receiver and transmitter FIFO.
0 = 32-Bit
1 = 64-Bit
26: M
ICROPROCESSOR
C
HANNEL
0-13 (0
F
UNCTION
R
54
EGISTER
X
01
H
-0
0
X
D1
X
01
H
)
H
B
IT
D
ESCRIPTION
By
Register
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(HW reset)
Default
Value
0
0
0
0
0
0
0
0