74LVCH162374APAG IDT, 74LVCH162374APAG Datasheet

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74LVCH162374APAG

Manufacturer Part Number
74LVCH162374APAG
Description
Flip Flops 16-bit Edge-Trig D-Type Flip-Flop
Manufacturer
IDT
Datasheet

Specifications of 74LVCH162374APAG

Rohs
yes
Number Of Circuits
1
Logic Family
74LVCH
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Propagation Delay Time
6.2 ns
Supply Voltage - Max
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-48
Minimum Operating Temperature
- 40 C
Supply Voltage - Min
3 V
Part # Aliases
IDT74LVCH162374APAG
FEATURES:
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2006 Integrated Device Technology, Inc.
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
machine model (C = 200pF, R = 0)
1
CLK
1
OE
CC
CC
D
1
= 3.3V ± 0.3V, Normal Range
= 2.7V to 3.6V, Extended Range
1
48
47
SK(o)
(Output Skew) < 250ps
TO SEVEN OTHER CHANNELS
1D
C1
3.3V CMOS 16-BIT
EDGE TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
2
1
Q
1
1
DESCRIPTION:
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The output enable (OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved noise margin.
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
2
2
CLK
2
The LVCH162374A 16-bit edge-triggered D-type flip-flop is built using
All pins of the LVCH162374A can be driven from either 3.3V or 5V
The LVCH162374A has series resistors in the device output structure
The LVCH162374A has “bus-hold” which retains the inputs’ last state
OE
D
1
36
25
24
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162374A
±
1D
C1
12mA at the designated thresholds.
JUNE 2006
DSC-4678/4
13
2
Q
1

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74LVCH162374APAG Summary of contents

Page 1

... SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 2006 Integrated Device Technology, Inc. 3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP- FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: The LVCH162374A 16-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology ...

Page 2

... IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP PIN CONFIGURATION GND GND GND ...

Page 3

... IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage Level IL I Input Leakage Current High Impedance Output Current ...

Page 4

... PLZ t Set-up Time HIGH or LOW, xDx before xCLK SU t Hold Time HIGH or LOW, xDx after xCLK H t xCLK Pulse Width HIGH or LOW W (2) t (o) Output Skew SK NOTES: 1. See TEST CIRCUITS AND WAVEFORMS Skew between any two outputs of the same package and switching in the same direction. ...

Page 5

... HIGH Enable and Disable Times DATA INPUT TIMING INPUT t REM CONTROL CONTROL Set-up, Hold, and Release Times LOW-HIGH-LOW PULSE t W HIGH-LOW-HIGH PULSE Pulse Width LVC Link PLZ V ...

Page 6

... H 74 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 6 INDUSTRIAL TEMPERATURE RANGE Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - Green 16-Bit Edge Triggered D-Type Flip-Flop Double-Density with Resistors, ±12mA Bus-hold -40°C to +85°C for Tech Support: logichelp@idt.com ...

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