MAX9123EUE+G60 Maxim Integrated, MAX9123EUE+G60 Datasheet - Page 3

• Manufacturer Part Number: MAX9123EUE+G60
• Description: LVDS Interface IC Quad LVDS Line Transmitter with Flow-Through Pinout
• Manufacturer: Maxim Integrated

SWITCHING CHARACTERISTICS
(V
otherwise noted.) (Notes 4, 5, 6)
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
Note 3: Guaranteed by correlation data.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: C
Note 6: Signal generator conditions for dynamic tests: V
Note 7: t
Note 8: t
Note 9: t
Note 10: t
Note 11: f
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew (Note 7)
Differential Channel-to-Channel
Skew (Note 8)
Differential Part-to-Part Skew
(Note 9)
Differential Part-to-Part Skew
(Note 10)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency
(Note 11)
CC
= +3.0V to +3.6V, R
at T
V
1ns (0% to 100%).
device.
of each other.
and temperature ranges.
100%). Transmitter output criteria: duty cycle = 45% to 55%, V
SKD4
SKD1
SKD2
SKD3
MAX
OD
PARAMETER
L
includes probe and jig capacitance.
A
.
signal generator conditions: V
= +25°C.
is the magnitude difference of differential propagation delay. t
is the magnitude difference of t
is the magnitude difference of any differential propagation delays between devices at the same V
is the magnitude difference of any differential propagation delays between devices operating over the rated supply
_______________________________________________________________________________________
L
= 100Ω ±1%, C
SYMBOL
t
t
t
t
t
t
f
PHLD
PLHD
SKD1
SKD2
SKD3
SKD4
t
t
t
t
t
t
MAX
PHZ
PZH
TLH
THL
PLZ
PZL
L
OL
= 15pF, T
PHLD
= 0, V
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 4 and 5
Figures 4 and 5
Figures 4 and 5
Figures 4 and 5
or t
OH
PLHD
A
Quad LVDS Line Driver with
OL
= 3V, f = 400MHz, 50% duty cycle, R
= -40°C to +85°C. Typical values are at V
= 0, V
of one channel to the t
CONDITIONS
OH
= 3V, f = 100MHz, 50% duty cycle, R
OD
≥ 250mV.
Flow-Through Pinout
SKD1
= |t
PHLD
PHLD
or t
- t
PLHD
PLHD
O
= 50Ω, t
MIN
of another channel on the same
400
0.7
0.7
0.2
0.2
|.
CC
= +3.3V, T
R
≤ 1ns, t
O
TYP
0.04
0.07
0.13
0.43
0.39
0.39
= 50Ω, t
2.7
2.7
2.3
2.3
CC
F
A
≤ 1ns (0% to
and within 5°C
MAX
= +25°C, unless
0.25
0.35
R
1.7
1.7
0.8
1.0
1.0
1.0
5
5
7
7
≤ 1ns, t
UNITS
MHz
F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
≤
3