74LVTH16501MTDX Fairchild Semiconductor, 74LVTH16501MTDX Datasheet

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74LVTH16501MTDX

Manufacturer Part Number
74LVTH16501MTDX
Description
TXRX 18BIT UNIV BUS 3ST 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVTHr
Datasheet

Specifications of 74LVTH16501MTDX

Logic Type
Universal Bus Transceiver
Number Of Circuits
18-Bit
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2001 Fairchild Semiconductor Corporation
74LVTH16501MEA
74LVTH16501MTD
74LVTH16501
Low Voltage 18-Bit Universal Bus Transceivers
with Bushold and 3-STATE Outputs
General Description
The LVTH16501 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16501 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16501 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500101
CC
Features
Input and output interface capability to systems at
5V V
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power up/down high impedance provides glitch-free bus
loading
Outputs source/sink 32 mA/ 64 mA
Functionally compatible with the 74 series 16501
ESD Performance:
Human-Body Model
Machine Model
Charged-Device Model
CC
Package Description
200V
2000V
1000V
March 2001
Revised March 2001
www.fairchildsemi.com

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74LVTH16501MTDX Summary of contents

Page 1

... MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation Features Input and output interface capability to systems ...

Page 2

Connection Diagram Functional Description For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If ...

Page 3

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...

Page 4

DC Electrical Characteristics Symbol Parameter V Input Clamp Diode Voltage IK V Input HIGH Voltage IH V Input LOW Voltage IL V Output HIGH Voltage OH V Output LOW Voltage OL I Bushold Input Minimum Drive I(HOLD) I Bushold Input ...

Page 5

AC Electrical Characteristics Symbol Parameter f CLKAB or CLKBA MAX t Propagation Delay PLH t Data to Outputs PHL t Propagation Delay PLH t LEBA or LEAB PHL t Propagation Delay PLH ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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