SLFLD25-3GBJ STEC, SLFLD25-3GBJ Datasheet - Page 4

• Manufacturer Part Number: SLFLD25-3GBJ
• Description: Solid State Drives - SSD 3GB 2.5-Inch
• Manufacturer: STEC

Specifications of SLFLD25-3GBJ

• Product Category: Solid State Drives - SSD
• Product: IDE Flash Drives
• Memory Size: 3 GB
• Sustained Read: 5 MB/s
• Sustained Write: 5 MB/s
• Active Mode Current: 30 mA
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Connector Type: 44-pin IDE
• Dimensions: 100.2 mm x 69.85 mm x 4 mm
• Minimum Operating Temperature: 0 C

SLFLD25-xxxJ(I)
Signal Description
-DASP
D15-D00
-IOWR
-IORD
INTRQ
A2-A0
-CS1, -CS2
-CSEL
-IOIS16
-PDIAG
-DREQ
-DACK
-IORDY
-RESET
VCC
GND
Key
Signal Name
I/O
I/O
I/O
Dir
—
—
—
O
O
O
O
I
I
I
I
I
I
I
18, 16, 14, 12,
5, 7, 9, 11, 13,
26, 30, 40, 43
10, 8, 6, 4, 3,
2, 19, 22, 24,
35, 33, 36
15, 17
37, 38
41, 42
Pin
39
23
25
31
28
32
34
21
29
27
20
1
This input/output is the Disk Active/Slave Present signal in the Master/
Slave handshake protocol.
All Task File operations occur in byte mode on the low order bus D00-D07
while all data transfers are 16 bit using D00-D15.
The I/O Write strobe pulse is used to clock I/O data on the drive Data
bus into the Drive controller registers when the Drive is configured to
use the I/O interface. The clocking will occur on the negative to
positive edge of the signal (trailing edge).
This is an I/O Read strobe generated by the host. This signal gates I/O
data onto the bus from the Drive.
Signal is the active high Interrupt Request to the host.
A[2:0] are used to select the one of eight registers in the Task File.
-CS1 is the chip select for the task file registers while -CS2 is used to select
the Alternate Status Register and the Device Control Register.
This internally pulled up signal is used to configure this device as a Master
or a Slave. When the pin is grounded, this device is configured as a Master.
When the pin is open, this device is configured as a Slave
Not used.
This input/output is the Pass Diagnostic signal in the Master/Slave
handshake protocol.
Not used.
Not used.
Not used, and pulled up to VCC through a 4.7K ohm resistor.
This input pin is the active low hardware reset from the host.
Power.
Ground.
This pin is keyed to ensure cable is connected with the proper orientation.
Document Part Number 61000-02817-109 March 2005
Description
IDE FLASH DRIVE
Page 4