MAX9665ETP+ Maxim Integrated, MAX9665ETP+ Datasheet - Page 30

• Manufacturer Part Number: MAX9665ETP+
• Description: LCD Gamma Buffers 6/8/10-Channel 10-Bit Nonvolatile Programmable Gamma and VCOM Reference Voltages
• Manufacturer: Maxim Integrated

6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
To program the MTP memory, apply the MTP program-
ming waveform through the CTL interface (Figure 11).
Unlike the MAX1512, the control interface only delivers
DAC adjustment commands, not programming power.
AVDD must be valid for MTP programming to occur. If
AVDD is not valid for MTP programming, the single-wire
interface is in shutdown.
To apply the MTP programming waveform, carefully
ramp CTL from midscale (DVDD/2) to the programming
voltage, V
ramp is generated digitally, use at least 45 steps to
achieve the required 320mV ramp resolution. During
the ramp time, VCOM adjustment is disabled and the
MTP cell is biased in preparation for programming.
After reaching V
the MTP program time, the MTP memory stores the
DAC setting. Next, drive CTL to ground in less than
1ms and hold for at least 200µs. Finally, drive CTL to
DVDD/2 to complete the write cycle. The MTP memory
is factory set to half scale. Follow the MTP program-
ming specification in Table 12 to guarantee reliable
MTP memory programming. Violating the specifications
can damage the MTP memory or affect data retention.
Table 12 shows the timing and voltage parameters for
MTP programming. This table is used for programming
through the single-wire interface.
The single-wire interface can be disabled to reduce the
DVDD supply current. Connect CE to GND to reduce the
typical supply current from 450µA to 320µA. Connect
CE to DVDD to enable the single-wire interface.
The programming circuit in Figure 12 drives CE high to
enable the CTL input when it is connected. When the
programming circuit is not connected, CE is pulled low
through resistor R
CTL input is relatively immune to noise and brief voltage
transients. It can be safely left continuously enabled if
higher supply current is acceptable.
Table 12. MTP Memory Programming Specifications
30
CTL Programming Voltage
CTL Programming Ramp
MTP Memory Program Time
V
Done Hold Time
P-P
______________________________________________________________________________________
Fall Time
PARAMETER
P-P
Single-Wire Interface Enable/Disable (CE)
, in 7.5ms as shown in Figure 11. If the
P-P
CE
, hold CTL at V
, which disables the CTL input. The
MTP Programming (CTL)
SYMBOL
P-P
V
T1
T2
T3
T4
P-P
for 1ms. During
15.25
MIN
200
7.0
0.9
10
Figure 11. MTP Memory Programming
Figure 12. Optional Circuit to Drive CE
DVDD/2
CTL VOLTAGE
V
P-P
PROGRAMMING
0
CIRCUIT
DVDD
TYP
15.5
7.5
1.0
—
—
T1
T2
R
CE
15.75
T3
MAX
1000
8.0
1.1
—
T4
CE
CTL
GND
MAX9665
MAX9666
MAX9667
UNITS
ms
ms
µs
µs
V
TIME