72V2101L15PFI IDT, 72V2101L15PFI Datasheet

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... LOGIC PRS IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...

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... FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. ...

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... During Master Reset (MRS) the following events occur: The read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The LD pin selects either a partial flag default ...

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... FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. In the IDT Standard mode, the EF function is selected. EF indicates whether or O not the FIFO memory is empty. In FWFT mode, the OR function is selected. ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating (2) V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

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... NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. ...

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... This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK ...

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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V2101/ 72V2111 has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 IDT72V2101 (262,144 x 9⎯BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 7FH LOW at Master Reset FFH HIGH at Master Reset 8 7 EMPTY OFFSET (MID-BYTE) REGISTER DEFAULT VALUE 00H LOW at Master Reset ...

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... NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 4. Programmable Flag Offset Programming Sequence SEN WCLK ...

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... IDT72V2111 in IDT Standard mode. In FWFT mode 262,145 for the IDT72V2101 and D = 524,289 for the IDT72V2111. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array ...

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... RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup, the PAE flag will be updated ...

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... HF goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW. ...

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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after after the valid WCLK cycle. D writes to the FIFO (D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. ...

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... In IDT Standard mode reads are performed after reset (MRS), PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (262,144-m) writes for the IDT72V2101 and (524,288-m) writes for the IDT72V2111. The offset “m” is the full offset value ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing 17 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t RSR t RSR If FWFT = HIGH HIGH ...

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... WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus SKEW1 of WCLK and the rising edge of RCLK is less than HIGH. 3. First word latency 1 SKEW1 RCLK REF Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) t CLK t CLKH t CLKL ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 COMMERCIAL AND INDUSTRIAL 20 TEMPERATURE RANGES ...

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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...

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... There must be at least two words written to the FIFO before a Retransmit operation can be invoked. WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V2101 and for the IDT72V2111. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes ENS ...

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... PAF offset . maximum FIFO depth. In IDT Standard mode 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. In FWFT mode 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...

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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. 2. For FWFT mode maximum FIFO depth 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

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... Use an AND gate in IDT Standard mode gate in FWFT mode not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 19. Block Diagram of 262,144 x 18 and 524,288 x 18 Width Expansion problems can be avoided by creating composite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of every FIFO ...

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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V2101 can easily be adapted to applications requiring depths greater than 262,144 and 524,288 for the IDT72V2111 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. ...

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... Industrial (-40°C to +85°C) Green Thin Plastic Quad Flatpack (TQFP, PN64-1) Commercial Only Clock Cycle Time (t Com'l & Ind'l Speed in Nanoseconds Commercial Only Low Power 262,144 x 9 — 3.3V SuperSyncFIFO 524,288 x 9 — 3.3V SuperSyncFIFO 4669 drw24 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ) CLK ...