72V36110L7-5PF IDT, 72V36110L7-5PF Datasheet - Page 47
![no-image](/images/no-image-200.jpg)
72V36110L7-5PF
Manufacturer Part Number
72V36110L7-5PF
Description
FIFO 128Kx36 3.3V SUPER SYNC II FIFO
Manufacturer
IDT
Datasheet
1.72V36110L6PFG.pdf
(48 pages)
Specifications of 72V36110L7-5PF
Part # Aliases
IDT72V36110L7-5PF
- Current page: 47 of 48
- Download datasheet (371Kb)
HIGH-IMPEDANCE
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
The optional High-Impedance instruction sets all outputs (including two-state
TM
36-BIT FIFO
47
BYPASS
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
The required BYPASS instruction allows the IC to remain in a normal
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
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