93LC46C-I/SN Microchip Technology, 93LC46C-I/SN Datasheet - Page 9
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93LC46C-I/SN
Manufacturer Part Number
93LC46C-I/SN
Description
IC EEPROM 1KBIT 3MHZ 8SOIC
Manufacturer
Microchip Technology
Specifications of 93LC46C-I/SN
Memory Size
1K (128 x 8 or 64 x 16)
Package / Case
8-SOIC (3.9mm Width)
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
3MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
64 x 16 or 128 K x 8
Interface Type
2-Wire
Maximum Clock Frequency
2 MHz
Access Time
6 ms
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
93LC46C-I/SNG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
93LC46C-I/SN
Manufacturer:
MICROCHIP
Quantity:
6 600
Company:
Part Number:
93LC46C-I/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
93LC46C-I/SN
Manufacturer:
MICROCHIP
Quantity:
6 600
Part Number:
93LC46C-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.6
The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded
by an Erase/Write Enable (EWEN) instruction. Once the
EWEN instruction is executed, programming remains
FIGURE 2-5:
FIGURE 2-6:
2.7
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.
FIGURE 2-7:
2010 Microchip Technology Inc.
CLK
CLK
CS
DO
CS
DI
CLK
DI
CS
DI
Erase/Write Disable and Enable
(EWDS/EWEN)
Read
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
High-Z
1
1
1
EWDS TIMING
EWEN TIMING
READ TIMING
1
0
0
0
0
0
A
N
0
1
•••
0
A0
1
0
Dx
x
x
•••
enabled until an EWDS instruction is executed or Vcc is
removed from the device.
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN and
EWDS instructions.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
•••
•••
D0
Dx
x
x
•••
T
T
CSL
CSL
D0
Dx
•••
DS21749H-page 9
D0
PD
).