DS26514G Maxim Integrated, DS26514G Datasheet - Page 67

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

9.9.9 Error Count Registers
The DS26514 contains four counters that are used to accumulate line coding errors, path errors, and
synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62.5ms (E1
mode only) or manually. See the Error Counter Configuration Register (ERCNT). When updated automatically, the
user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at
their respective maximum counts and they will not roll over. (Note: Only the Line Code Violation Count Register
has the potential to overflow but the bit error would have to exceed 10E-2 before this would occur.)
The DS26514 can share the one-second timer from Port 1 across all ports. All DS26514 error/performance
counters can be configured to update on the shared one-second source or a separate manual update signal input.
See the
counters, the host software can be streamlined to read and process performance information from multiple spans in
a more controlled manner.
9.9.9.1 Line Code Violation Count Register (LCVCR)
Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of
the same polarity. In T1 mode, if the B8ZS mode is set for the receive side, then B8ZS codewords are not counted
as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as
BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU-T O.161. Code violations are
defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be
programmed to count BPVs when receiving AMI code and to count CVs when receiving B8ZS or HDB3 code. This
counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and
will not rollover. The bit error rate on an E1 line would have to be greater than 10E-2 before the VCR would
saturate. See
Table 9-28. T1 Line Code Violation Counting Options
Table 9-29. E1 Line Code Violation Counting Options
19-5856; Rev 4; 5/11
COUNT EXCESSIVE ZEROS?
ERCNT
(ERCNT.0)
E1 CODE VIOLATION SELECT
Table 9-28
Yes
Yes
No
No
register for more information. By allowing multiple framer cores to synchronously latch their
(ERCNT.0)
and
0
1
Table 9-29
B8ZS ENABLED?
for details of exactly what the LCVCRs count.
(RCR1.6)
Yes
Yes
No
No
BPVs (B8ZS/HDB3 codewords not counted)
BPVs + 16 consecutive zeros
IN LCVCR1,
BPVs + 8 consecutive zeros
WHAT IS COUNTED
DS26514 4-Port T1/E1/J1 Transceiver
IN LCVCR1,
WHAT IS COUNTED
BPVs
CVs
BPVs
LCVCR2
LCVCR2
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