DS2151QNB+ Maxim Integrated, DS2151QNB+ Datasheet - Page 4

• Manufacturer Part Number: DS2151QNB+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2151QNB+

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V
• Part # Aliases: 90-2151Q+NB0

DS2151Q
1 DETAILED DESCRIPTION
The DS2151Q T1 single-chip transceiver (SCT) contains all the necessary functions for connection to T1
lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line
build-outs as well as CSU build-outs of -7.5dB, -15dB, and -22.5dB. The on-board jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of 64
8-bit internal registers that the user can access to control the operation of the unit. Quick access via the
parallel control port allows a single micro to handle many T1 lines. The device fully meets all of the latest
T1 specifications including ANSI T1.403-199X, AT&T TR 62411 (12-90), and ITU G.703, G.704,
G.706, G.823, and I.431.
1.1 Introduction
The analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of
the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered T1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2151Q is totally independent from the receive side in both the clock
requirements and characteristics. Data can be either provided directly to the transmit formatter or via an
elastic store. The transmit formatter will provide the necessary data overhead for T1 transmission. Once
the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the
waveshaping and line driver functions. The DS2151Q will drive the T1 line from the TTIP and TRING
pins via a coupling transformer.
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