DS2155GB Maxim Integrated, DS2155GB Datasheet - Page 96

• Manufacturer Part Number: DS2155GB
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2155GB

• Part # Aliases: 90-2155G-B00

17.
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive
directions. When operated in the T1 mode, only the first 24 channels are used by the DS2155, the
remaining channels, CH25–CH32, are not used.
The DS2155 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the
per-channel idle code register (PCICR). The contents of the array contain the idle codes to be substituted
into the appropriate transmit or receive channels. This substitution can be enabled and disabled on a per-
channel basis by the transmit-channel idle code-enable registers (TCICE1–4) and receive-channel idle
code-enable registers (RCICE1–4).
To program idle codes, first select a channel by writing to the IAAR register. Then write the idle code to
the PCICR register. For successive writes there is no need to load the IAAR with the next consecutive
address. The IAAR register automatically increments after a write to the PCICR register. The auto
increment feature can be used for read operations as well. Bits 6 and 7 of the IAAR register can be used
to block write a common idle code to all transmit or receive positions in the array with a single write to
the PCICR register. Bits 6 and 7 of the IAAR register should not be used for read operations. TCICE1–4
and RCICE1–4 are used to enable idle code replacement on a per-channel basis.
Table 17-A. Idle-Code Array Address Mapping
BITS 0 to 5 OF IAAR
PER-CHANNEL IDLE CODE GENERATION
REGISTER
—
—
30
31
32
33
34
—
—
62
63
0
1
2
MAPS TO CHANNEL
Transmit Channel 31
Transmit Channel 32
Receive Channel 31
Receive Channel 32
Transmit Channel 1
Transmit Channel 2
Transmit Channel 3
Receive Channel 1
Receive Channel 2
Receive Channel 3
—
—
—
—
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