72V2105L10PF IDT, 72V2105L10PF Datasheet - Page 8

• Manufacturer Part Number: 72V2105L10PF
• Description: FIFO 256Kx18 3.3V SUPERSYNC FIFO
• Manufacturer: IDT

Specifications of 72V2105L10PF

• Part # Aliases: IDT72V2105L10PF

PROGRAMMING FLAG OFFSETS
IDT72V295/72V2105 has internal registers for these offsets. Default set-
tings are stated in the footnotes of Table 1 and Table 2. Offset values can
be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines whether serial
or parallel flag offset programming is enabled. A HIGH on LD during Master
Reset selects serial loading of offset values and in addition, sets a default
PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary), and a default PAF offset value of 3FFH (a threshold 1,023 words
from the full boundary). A LOW on LD during Master Reset selects parallel
loading of offset values, and in addition, sets a default PAE offset value of
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TABLE II ⎯ STATUS FLAGS FOR FWFT MODE
TABLE I ⎯ STATUS FLAGS FOR IDT STANDARD MODE
Full and Empty Flag offset values are user programmable. The
Number of
Words in
FIFO
Number of
Words in
FIFO
(
1)
TM
131,072 x 18, 262,144 x 18
65,538 to (131,073-(m+1))
65,537 to (131,072-(m+1))
(131,072-m)
(131,073-m)
(n+1) to 65,536
(n+2) to 65,537
IDT72V295
1 to n
IDT72V295
131,072
1 to n+1
131,073
0
0
(2)
to 131,072
(1)
to 131,071
(1)
(2)
131,074 to (262,145-(m+1))
131,073 to (262,144-(m+1))
(262,144-m)
(262,145-m)
8
07FH (a threshold 127 words from the empty boundary), and a default PAF
offset value of 07FH (a threshold 127 words from the full boundary). See
Figure 3, Offset Register Location and Default Values.
the current offset values. It is only possible to read offset values via parallel
read.
rizes the control pins and sequence for both serial and parallel programming
modes. For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming
has been selected.
(n+2) to 131,073
In addition to loading offset values into the FIFO, it also possible to read
Figure 4, Programmable Flag Offset Programming Sequence, summa-
The offset registers may be programmed (and reprogrammed) any time
(n+1) to 131,072
IDT72V2105
1 to n+1
IDT72V2105
262,145
1 to n
262,144
0
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
0
(2)
to 262,144
(1)
to 262,143
(1)
(2)
FF
IR
H
H
H
H
H
L
L
L
L
L
H
L
PAF HF
PAF HF PAE
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
PAE OR
4668 drw 05
H
H
H
H
L
L
H
H
H
H
L
L
EF
H
H
H
H
H
H
L
L
L
L
L
L