72V291L15PF IDT, 72V291L15PF Datasheet
72V291L15PF
Specifications of 72V291L15PF
Related parts for 72V291L15PF
72V291L15PF Summary of contents
Page 1
... LOGIC PRS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
Page 2
... There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed ...
Page 3
... During Master Reset (MRS) the following events occur: The read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The LD pin selects either a partial flag default setting of 127 with parallel programming or a partial flag default setting of 1,023 with serial programming ...
Page 4
... FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. In the IDT Standard mode, the EF function is selected. EF indicates whether or O not the FIFO memory is empty. In FWFT mode, the OR function is selected. ...
Page 5
... IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
Page 6
... SKEW3 for EF/OR NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 15ns speed grade is available as a standard device. 3. Pulse widths less than minimum values are not allowed. 4. Values guarenteed by design, not currently tested. ...
Page 7
... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 65,537 writes for the IDT72V281 and 131,073 writes for the IDT72V291, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register ...
Page 8
... It is only possible to read offset values via parallel read. Figure 4, Programmable Flag Offset Programming Sequence, summa- rizes the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows. TABLE 1 ⎯ STATUS FLAGS FOR IDT STANDARD MODE Number of (n+1) to 32,768 Words in ...
Page 9
... X NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 4. Programmable Flag Offset Programming Sequence ...
Page 10
... WCLK edges plus t rising RCLK edges plus t The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q pins when LD is set LOW and REN is set LOW. For the IDT72V281 ...
Page 11
... words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 65,536 for the IDT72V281 and D = 131,072 for the IDT72V291 in IDT Standard mode. In FWFT mode 65,537 for the IDT72V281 and D = 131,073 for the IDT72V291 ...
Page 12
... HF goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW. ...
Page 13
... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 65,537 for the IDT72V281 and after the valid WCLK cycle. 131,073 for the IDT72V291) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...
Page 14
... RCLK edge that accom- plishes this condition sets HF HIGH. In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO, where D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291. ...
Page 15
... IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSS t If FWFT = HIGH HIGH RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW ...
Page 16
... IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing 16 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t RSR t RSR If FWFT = HIGH HIGH ...
Page 17
... WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus SKEW3 of WCLK and the rising edge of RCLK is less than HIGH. 3. First data word latency: 60ns + t + 1*T . REF RCLK Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode CLK t CLKH t CLKL 2 t ...
Page 18
... IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
Page 19
... IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
Page 20
... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V281 and 131,072 for the IDT72V291 goes HIGH at 60ns + 1 RCLK cycle + t . ...
Page 21
... OR goes LOW at 60ns + 2 RCLK cycles + t . REF WCLK t ENS SEN t LDS BIT 0 NOTE for the IDT72V281 and for the IDT72V291. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF t ...
Page 22
... ENS ENH REN DATA IN OUTPUT REGISTER 0 7 NOTE LOW Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V291 TM t LDH t ENH t DH PAE OFFSET PAF OFFSET (MSB) (LSB) PAE OFFSET PAF OFFSET ...
Page 23
... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 65,536 for the IDT72V281 and 131,072 for the IDT72V291. 2. For FWFT mode maximum FIFO depth 65,537 for the IDT72V281 and 131,073 for the IDT72V291. Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
Page 24
... Use an AND gate in IDT Standard mode gate in FWFT mode not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion ...
Page 25
... IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72V281 72V291 n DATA IN Dn Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion For a full expansion configuration, the amount of time it takes for IR of the first ...
Page 26
... Thin Plastic Quad Flatpack (TQFP, PN64-1) Slim Thin Quad Flatpack (STQFP, PP64-1) Commercial Only Clock Cycle Time (t Com'l & Ind'l Speed in Nanoseconds Commercial Only Low Power 65,536 x 9 3.3V — SuperSyncFIFO 131,072 x 9 3.3V — SuperSyncFIFO 4513 drw 26 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ) CLK ...