MR25H256MDFR Everspin Technologies, MR25H256MDFR Datasheet
MR25H256MDFR
Specifications of MR25H256MDFR
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MR25H256MDFR Summary of contents
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... DEVICE PIN ASSIGNMENT......................................................................... 3 2. SPI COMMUNICATIONS PROTOCOL...................................................... 4 3. ELECTRICAL SPECIFICATIONS................................................................. 10 4. TIMING SPECIFICATIONS.......................................................................... 14 5. ORDERING INFORMATION....................................................................... 16 6. MECHANICAL DRAWING.......................................................................... 17 7. REVISION HISTORY...................................................................................... 18 How to Reach Us.......................................................................................... 18 Everspin Technologies © 2012 1 MR25H256 Rev. 8, 10/2012 MR25H256 256Kb Serial SPI MRAM DFN Small Flag DFN ...
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... SCK SI System Configuration Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are com- mon among devices. Each device requires CS and HOLD pins to be driven separately. Everspin Technologies © 2012 Figure 1.1 Block Diagram Instruction Decode Clock Generator Control Logic ...
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... Input Serial Input SCK 6 Input Serial Clock HOLD 7 Input Hold V 8 Supply Power Supply DD Everspin Technologies © 2012 Figure 1.3 Pin Diagrams (Top View 8-Pin DFN or 8-Pin DFN Small Flag Packages Table 1.1 Pin Functions Description An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z ...
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... All bits in the status register are pre-set from the factory to the “0” state. Bit 7 Bit 6 SRWD Don’t Care Don’t Care Everspin Technologies © 2012 Table 2.1 Command Codes Binary Code Hex Code 0000 0110 0000 0100 ...
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... The RDSR command is entered by driving CS low, sending the command code, and then driving CS high SCK High Impedance Everspin Technologies © 2012 Table 2.3 Block Memory Write Protection Memory Contents Protected Area None Upper Quarter Upper Half All Table 2.4 Memory Protection Modes Protected Blocks Unprotected Blocks Protected ...
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... WRSR command is not executed unless the Write Enable Latch (WEL) has been set executing a WREN command while pin WP and bit SRWD correspond to values that make the status register writable as seen in table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0 upon power cycling. Everspin Technologies © 2012 Figure 2.2 WREN 0 ...
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... The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi- nated by bring CS high SCK Instruction (03h Everspin Technologies © 2012 Figure 2.4 WRSR Instruction (01h ...
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... SCK Instruction (02h SCK Data Byte MSB SO Everspin Technologies © 2012 Figure 2.6 WRITE 16-Bit Address MSB High Impedance Data Byte 3 2 ...
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... The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after SCK Everspin Technologies © 2012 Figure 2.7 SLEEP Instruction (B9h ...
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... Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced than 0.5V. The AC value less than 20mA. Power dissipation capability depends on package characteristics and use environment. 3 Everspin Technologies © 2012 Table 3.1 Absolute Maximum Ratings Conditions All 2 All 2 ...
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... Active Write Current DDW I Standby Current SB I Standby Sleep Mode Current ZZ I current is specified with CS high and the SPI bus inactive Everspin Technologies © 2012 Table 3.2 Operating Conditions Grade Industrial AEC-Q100 Grade1 All All Industrial AEC-Q100 Grade 1 1 Table 3.3 DC Characteristics ...
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... Output load for low and high impedance parameters Output load for all other timing parameters Figure 4.1 Output Load for Impedance Parameter Measurements Output Figure 4.2 Output Load for all Other Parameter Measurements Everspin Technologies © 2012 Table 4.1 Capacitance Table 4.2 AC Measurement Conditions ...
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... V (max (min) DD Reset state of the device V WI Everspin Technologies © 2012 = 400 μs after power up. Users must wait this time PU so that the signal tracks the power supply during power-up DD Table 4.3 Power-Up Min 2.2 400 Figure 4.3 Power-Up Timing Chip Selection not allowed ...
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... WP Setup To CS Low WPS t WP Hold From CS High WPH t Sleep Mode Entry Time DP t Sleep Mode Exit Time RDP t Output Disable Time DIS Over the Operating Temperature Range and C 1 Everspin Technologies © 2012 Table 4.4 AC Timing Parameters Conditions 3.6v 3 3.6v 3 3.6v. ...
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... TIMING SPECIFICATIONS CSS V IH SCK High Impedance SCK HOLD SO Everspin Technologies © 2012 Figure 4.4 Synchronous Data Timing Figure 4.5 HOLD Timing MR25H256 CSH ...
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... ORDERING INFORMATION MR 25H 256 Grade Temperature Package Industrial -40 to +85 C AEC-Q100 Grade 1 -40 to +125 C Everspin Technologies © 2012 Figure 5.1 Part Numbering System C DC Package Options DC 8 Pin DFN on Tray DCR 8 Pin DFN on Tape and Reel DF 8 pin DFN Small Flag on Tray ...
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... Max. 5.10 6.10 1.00 Min. 4.90 5.90 0.90 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229-E Everspin Technologies © 2012 Figure 6.1 DFN Package Detail 1.27 0.45 0.05 0.35 0.70 BSC 0.35 0.00 Ref ...
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... Min 4.90 5.90 0.80 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229-E Everspin Technologies © 2012 Figure 6.2 DFN Small Flag Package Detail 1.27 0.45 0.05 1.60 BSC 0 ...
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... All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended ...