MR25H10MDF Everspin Technologies, MR25H10MDF Datasheet

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FEATURES • No write delays • Unlimited write endurance • Data retention greater than 20 years • Automatic data protection on power loss • Block write protection • Fast, simple SPI interface with MHz clock rate • 2.7 to 3.6 Volt power supply range • Low current sleep mode • Industrial temperatures • Available in 8-pin DFN or 8-pin DFN Small Flag RoHS-compliant packages • Direct replacement for serial EEPROM, Flash, FeRAM • AEC-Q100 Grade 1 Option INTRODUCTION The MR25H10 is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. The MR25H10 offers serial EEPROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between writes. The MR25H10 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins. The MR25H10 is available in either 8-pin DFN package 8-pin DFN Small Flag package. Both are compatible with serial EEPROM, Flash, and FeRAM products. The MR25H10 provides highly reliable data storage over a wide range of temperatures. The product is ...

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DEVICE PIN ASSIGNMENT Overview The MR25H10 is a serial MRAM with memory array logically organized as 128Kx8 using the four pin in- terface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash components allowing MRAM to replace these components in the same socket and interoperate on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and more reliable data retention compared to available serial memory alternatives HOLD SCK SI System Configuration Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are common among devices. Each device requires CS and HOLD pins to be driven separately. Everspin Technologies © 2012 Figure 1.1 Block Diagram Instruction Decode Clock Generator Control Logic Write Protect Instruction Register 17 Address Register Counter ...

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DEVICE PIN ASSIGNMENT Signal Name Pin I Input SO 2 Output WP 3 Input V 4 Supply Input SCK 6 Input HOLD 7 Input V 8 Supply DD Everspin Technologies © 2012 Figure 1.3 Pin Diagrams (Top ...

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SPI COMMUNICATIONS PROTOCOL MR25H10 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. De- pending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or aborted accesses. Instruction Description WREN Write Enable WRDI Write Disable RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes WRITE Write Data Bytes SLEEP Enter Sleep Mode WAKE Exit Sleep Mode Status Register ...

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SPI COMMUNICATIONS PROTOCOL Status Register BP1 BP0 WEL SRWD Low 1 1 High When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status register bits BP0 and BP1 can be modified. Once SRWD is set must be high to modify SRWD, BP0 and BP1. Read Status Register (RDSR) The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be read at any time to check the status of write enable latch bit, status register write protect bit, and block ...

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SPI COMMUNICATIONS PROTOCOL Write Enable (WREN) The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The WEL bit must be set prior to writing in the status register or the memory. The WREN command is entered by driving CS low, sending the command code, and then driving CS high. CS Mode 3 SCK Mode Write Disable (WRDI) The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending the command code, and then driving CS high. The WEL bit is reset power-up or completion of WRDI. CS Mode 3 SCK Mode Write Status Register (WRSR) The Write Status Register (WRSR) command allows new values to be written to the Status Register. The WRSR command is not executed unless the Write Enable Latch (WEL) has been set executing a WREN command while pin WP and bit SRWD correspond to values that make the status register writable ...

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SPI COMMUNICATIONS PROTOCOL The WRSR command is entered by driving CS low, sending the command code and status register write data byte, and then driving CS high.The WRSR command is entered by driving CS low, sending the com- mand code and status register write data byte, and then driving CS high. CS SCK SI SO Read Data Bytes (READ) The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are read out sequen- tially from memory until the read operation is terminated by bringing CS high The entire memory can be read in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi- nated by bring CS high SCK Instruction (03h Everspin Technologies © 2012 ...

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SPI COMMUNICATIONS PROTOCOL Write Data Bytes (WRITE) The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are written sequen- tially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in mem- ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory ideal for both program and data storage. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high SCK Instruction (02h ...

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SPI COMMUNICATIONS PROTOCOL Enter Sleep Mode (SLEEP) The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com- mand code, and then driving CS high. The standby current is achieved after time SCK Exit Sleep Mode (WAKE) The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after SCK Everspin Technologies © 2012 Figure 2.7 SLEEP 2 3 ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the field intensity specified in the maximum ratings. Symbol Parameter V Supply voltage DD V Voltage on any pin IN I Output current per pin OUT P Package power dissipation D T Temperature under bias BIAS T Storage Temperature stg T Lead temperature Lead H Maximum magnetic field exposure max_write H Maximum magnetic field exposure max_read ...

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ELECTRICAL SPECIFICATIONS Symbol Parameter V Power supply voltage DD V Input high voltage IH V Input low voltage IL T Temperature under bias A AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years 1 out of 20-year life.) Symbol Parameter I Input leakage current LI I Output leakage current LO V Output low voltage OL V Output high voltage OH Symbol Parameter I Active Read Current DDR I Active Write Current ...

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TIMING SPECIFICATIONS Symbol Parameter C Control input capacitance In C Input/Output capacitance I/O ƒ = 1.0 MHz 3 °C, periodically sampled rather than 100% tested Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Figure 4.1 Output Load for Impedance Parameter Measurements Output Figure 4.2 Output Load for all Other Parameter Measurements ...

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TIMING SPECIFICATIONS Power-Up Timing The MR25H10 is not accessible for a start-up time, t from the time when V (min) is reached until the first CS low to allow internal voltage references to become DD stable. The CS signal should be pulled sequence. Symbol Parameter V Write Inhibit Voltage WI t Startup Time (max (min) DD Reset state of the device V WI Everspin Technologies © 2012 = 400 μs after power up. Users must wait this time PU so that the signal tracks the power supply during power-up DD ...

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TIMING SPECIFICATIONS Synchronous Data Timing Symbol Parameter f SCK Clock Frequency SCK t Input Rise Time RI t Input Fall Time RF t SCK High Time WH t SCK Low Time WL Synchronous Data Timing (See figure 4. High Time Setup Time CSS t CS Hold Time CSH t Data In Setup Time SU t Data In Hold Time ...

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TIMING SPECIFICATIONS CSS V IH SCK High Impedance SCK HOLD SO Everspin Technologies © 2012 Figure 4.4 Synchronous Data Timing ...

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ORDERING INFORMATION MR 25H Temperature Grade Range Industrial -40 to +85 C AEC-Q100 Grade 1 -40 to +125 C Everspin Technologies © 2012 Figure 5.1 Part Numbering System Package Options DC 8 Pin DFN on Tray DCR 8 Pin DFN on Tape and Reel DF 8 ...

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MECHANICAL DRAWINGS A B Pin 1 Index Dimension Max. 5.10 6.10 1.00 Min. 4.90 5.90 0.90 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Everspin Technologies © 2012 Figure 6.1 DFN Package Detail ...

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MECHANICAL DRAWINGS A B Pin 1 Index Dimension Max 5.10 6.10 0.90 Min 4.90 5.90 0.80 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Everspin Technologies © 2012 Figure 6.2 Small Flag DFN ...

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... Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inci- dental damages. “ ...