DS1225Y-200IND Maxim Integrated, DS1225Y-200IND Datasheet - Page 6
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DS1225Y-200IND
Manufacturer Part Number
DS1225Y-200IND
Description
NVRAM 64k Nonvolatile SRAM
Manufacturer
Maxim Integrated
Datasheet
1.DS1225Y-200IND.pdf
(8 pages)
Specifications of DS1225Y-200IND
Data Bus Width
8 bit
Memory Size
64 Kbit
Organization
8 K x 8
Interface Type
Parallel
Access Time
200 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Operating Current
85 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
EDIP-28
Mounting Style
Through Hole
Part # Aliases
90-1225Y-00I
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS1225Y-200IND
Manufacturer:
DALLAS
Quantity:
20 000
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V
3. t
4. t
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
NOT RECOMMENDED FOR NEW DESIGNS
PARAMETER
V
V
PARAMETER
Expected Data Retention Time
CE at V
CE at V
CC
CC
state.
going low to the earlier of CE or WE going high.
Cycle 1, the output buffers remain in a high-impedance state during this period.
buffers remain in a high-impedance state during this period.
WP
DS
Slew from V
Slew from 0V to V
is measured from the earlier of CE or WE going high.
is specified as the logical AND of CE and WE . t
IH
IH
IH
before Power-Down
after Power-Up
or V
IL
TP
. If OE = V
to 0V
TP
IH
during a write cycle, the output buffers remain in a high impedance
SYMBOL
SYMBOL
t
t
t
REC
t
t
PD
DR
F
R
6 of 8
MIN
MIN
100
10
0
0
WP
is measured from the latter of CE or WE
MAX
MAX
2
UNITS
UNITS
years
ms
µs
µs
µs
(T
A
NOTES
NOTES
= +25°C)
11
9
DS1225Y