72255LA20TF IDT, 72255LA20TF Datasheet - Page 25

• Manufacturer Part Number: 72255LA20TF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72255LA20TF

• Part # Aliases: IDT72255LA20TF

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 8,192 and 16,384 for the IDT72265LA with an 18-bit bus
width. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no
external logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with each single
FIFO. Figure 24 shows a depth expansion using two IDT72255LA/72265LA
devices.
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down")
until it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO's outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
RCLK period. Note that extra cycles should be added for the possibility
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
The IDT72255LA can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all
For an empty expansion configuration, the amount of time it takes for OR
where N is the number of FIFOs in the expansion and T
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
n
(N – 1)*(4*transfer clock) + 3*T
Dn
WCLK
Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion
FWFT/SI
72255LA
72265LA
IDT
•
TRANSFER CLOCK
RCLK
RCLK
Qn
RCLK
is the
•
GND
25
n
that the t
or RCLK and transfer clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
WCLK period. Note that extra cycles should be added for the possibility
that the tSKEW1 specification is not met between RCLK and transfer clock,
or WCLK and transfer clock, for the IR flag.
ever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
The "ripple down" delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the
where N is the number of FIFOs in the expansion and T
The Transfer Clock line should be tied to either WCLK or RCLK, which-
SKEW3
specification is not met between WCLK and transfer clock,
WCLK
Dn
(N – 1)*(3*transfer clock) + 2 T
FWFT/SI
72255LA
72265LA
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
TEMPERATURE RANGES
Qn
WCLK
JANUARY 13, 2009
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
READ CLOCK
DATA OUT
4670 drw 23
WCLK
is the