24C02C-I/P Microchip Technology, 24C02C-I/P Datasheet - Page 4

• Manufacturer Part Number: 24C02C-I/P
• Description: IC EEPROM 2KBIT 400KHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 24C02C-I/P

• Memory Size: 2K (256 x 8)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24C02C
2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
This input is used to synchronize the data transfer from
and to the device.
2.3
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either V
V
2.4
This is the hardware write-protect pin. It must be tied to
V
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.
2.5
The 24C02C employs a V
which disables the internal erase/write logic if the V
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
DS21202D-page 4
Vss
SDA
SCL
V
A0, A1, A2
WP
SS
CC
CC
.
or V
Name
SS
PIN DESCRIPTIONS
SDA Serial Data
SCL Serial Clock
A0, A1, A2
WP
Noise Protection
. If tied to Vcc, the hardware write protection
CC
(typical 10 k
PIN FUNCTION TABLE
Ground
Serial Data
Serial Clock
+4.5V to 5.5V Power Supply
Chip Selects
Hardware Write-Protect
CC
threshold detector circuit
Function
for 100 kHz, 2 k
CC
for
CC
or
3.0
The 24C02C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the Start
and Stop conditions, while the 24C02C works as slave.
Both master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.
FUNCTIONAL DESCRIPTION
 2003 Microchip Technology Inc.