XRT91L34ES Exar, XRT91L34ES Datasheet

XRT91L34ES

Manufacturer Part Number

XRT91L34ES

Description

Peripheral Drivers & Components - PCIs 4 CHOC12/STM4 OC3/STM1 CDR

Manufacturer

Exar

Datasheet

1.XRT91L34ES.pdf (38 pages)

Specifications of XRT91L34ES

Product Category

Peripheral Drivers & Components - PCIs

Rohs

yes

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Download datasheet (300Kb)

OCTOBER 2007

GENERAL DESCRIPTION

The XRT91L34 is a fully integrated quad channel

multirate Clock and Data Recovery (CDR) device for

SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52

Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0

applications. The device provides Clock and Data

Recovery (CDR) function by synchronizing its on-chip

Voltage Controlled Oscillator (VCO) to the incoming

serial data stream. The device internally monitors

Loss of Lock (LOL) conditions and automatically

mutes recovered data upon Loss of Signal (LOS)

conditions.

The clock and data recovery (CDR) unit accepts the

high speed NRZ serial data from the LVDS or

Differential LVPECL receiver and generates a clock

that is the same frequency as the incoming data. The

CDR block uses a reference clock to train and

monitor its clock recovery PLL. All four channels

share a single 77.76MHz or 19.44MHz reference

clock. Upon startup, the PLL locks to the local

reference clock. Once this is achieved, the PLL

Exar

IGURE

LOCK AND

Corporation 48720 Kato Road, Fremont CA, 94538

1. B

RESET

HOST /HW

DLOSDIS /SDI

CDRDIS0

DATA0RATE1

DATA0RATE0

INT

SDEXT0

POL0

LOCK

RXDI0N

RXDI0P

ATA

SCLK

SDO

ECOVERY

IAGRAM OF

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

LVDS/LVPECL

Input Drivers

100

Serial Proccesor

DLOSDIS

SDI

RX LOOP

Interface

FILTER

Channel Control Block

VERVIEW

XRT91L34

RXDATAIN

XRT91L34

Global Control Block

Clock and Data

CDR

STS-12/3/1

STM-4/1/0

Recovery

•

DLOS

(510) 668-7000

DLOSDIS

attempts to lock onto the incoming receive serial data

stream. Whenever the recovered clock frequency

deviates from the local reference clock frequency by

more than approximately ±500 ppm, the clock

recovery PLL will switch and lock back onto the local

reference clock and declare a Loss of Lock.

Whenever a Loss of Lock or a Loss of Signal event

occurs, the CDR will continue to supply a recovered

clock (based on the local reference) to the framer/

mapper device. When the SDEXT is de-asserted by

the optical module or when internal DLOS is

asserted, the receive serial data output will be forced

to a logic zero state for the entire duration that a LOS

condition is declared. This acts as a receive data

mute upon LOS function to prevent random noise

from being misinterpreted as valid incoming data.

When the SDEXT becomes active and the recovered

clock is determined to be within ±500 ppm accuracy

with respect to the local reference source and LOS is

no longer declared, the clock recovery PLL will switch

and lock back onto the incoming receive serial data

stream.

XRT91L34.

Figure 1

RECVD-

DATAOUT

RECVD-

CLKOUT

LVDS/LVPECL LEVEL SELECT

REFCLKN

REFCLKP

•

FAX (510) 668-7017

RCLKDIS0

HOST MODE

Channel 0

ONLY

Channel 1

shows the block diagram of the

19.44 / 77.76 MHz

Channel 2

Channel 3

LVDS/LVPECL

Output Drivers

XRT91L34

•

CDRREFSEL

TTLREFCLK

www.exar.com

RXDO0P

RXDO0N

RXCLKO0P

RXCLKO0N

OUTCFG

LOL0

TEST

REV. 1.0.1

Related parts for XRT91L34ES

XRT91L34ES Summary of contents

Page 1

... CLKOUT Recovery DLOSDIS DLOS • • (510) 668-7000 FAX (510) 668-7017 XRT91L34 REV. 1.0.1 shows the block diagram of the TEST OUTCFG CDRREFSEL 19.44 / 77.76 MHz TTLREFCLK RCLKDIS0 LVDS/LVPECL Output Drivers RXDO0P 0 RXDO0N 1 RXCLKO0P 0 RXCLKO0N 1 HOST MODE ONLY LOL0 Channel 0 Channel 1 Channel 2 Channel 3 • www.exar.com ...

Page 2

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR APPLICATIONS SONET/SDH-based Transmission Systems Add/Drop Multiplexers Cross Connect Equipment ATM and Multi-Service Switches, Routers and Switch/Routers DSLAMS SONET/SDH Test Equipment DWDM Termination Equipment FEATURES Quad Channel CDR targeted for SONET STS-12/STS-3/STS-1 ...

Page 3

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0 128 LQFP P IGURE n/c 1 n/c 2 RXDI0P 3 RXDI0N 4 VDD_IO 5 VDD_IO 6 GND_IO 7 GND_IO 8 n/c 9 n/c 10 RXDI1P 11 RXDI1N 12 ...

Page 4

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR GENERAL DESCRIPTION ................................................................................................. XRT91L34 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF APPLICATIONS ...........................................................................................................................................2 ......................................................................................................................................................2 FEATURES F 2. 128 LQFP P O IGURE THE ORDERING INFORMATION.....................................................................................................................3 ...

Page 5

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 5.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... ABLE ICROPROCESSOR NTERFACE ABLE ICROPROCESSOR NTERFACE T 10 ABLE ICROPROCESSOR NTERFACE T ...

Page 6

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR PIN DESCRIPTIONS HARDWARE CONTROL AME EVEL RESET LVTTL, LVCMOS TEST LVTTL, LVCMOS DATA0RATE[1:0] LVTTL, LVCMOS DATA1RATE[1:0] LVTTL, LVCMOS DATA2RATE[1:0] LVTTL, LVCMOS DATA3RATE[1:0] LVTTL, LVCMOS P YPE IN I ...

Page 7

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0 AME EVEL CDRREFSEL LVTTL, LVCMOS OUTCFG LVTTL, LVCMOS CDRDIS0 LVTTL, CDRDIS1 LVCMOS CDRDIS2 CDRDIS3 P YPE IN I 119 Clock and Data Recovery Unit Reference Frequency Select ...

Page 8

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR AME EVEL DLOSDIS LVTTL, /SDI LVCMOS POL0 LVTTL, POL1 LVCMOS POL2 POL3 SDEXT0 LVTTL, SDEXT1 LVCMOS, SDEXT2 SDEXT3 REFCLKP LVDS, REFCLKN Diff LVPECL TTLREFCLK LVTTL, LVCMOS P YPE ...

Page 9

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 RECEIVER SECTION AME EVEL RXDI0P LVDS, RXDI0N Diff LVPECL RXDI1P RXDI1N RXDI2P RXDI2N RXDI3P RXDI3N RXDO0P LVDS, RXDO0N Diff LVPECL RXDO1P RXDO1N RXDO2P RXDO2N RXDO3P RXDO3N RXCLKO0P ...

Page 10

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR POWER AND GROUND N T AME YPE AVDD1.8 PWR 42, 57, 58, 104, 105, DVDD1.8 PWR 51, 112 VDD_IO PWR 5, 6, 13, 14, 19, 20, 27, 28, 65, 66, 73, ...

Page 11

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 SERIAL MICROPROCESSOR INTERFACE AME EVEL YPE HOST/HW LVTTL, I LVCMOS CS LVTTL, I LVCMOS SCLK LVTTL, I LVCMOS DLOSDIS LVTTL, I /SDI LVCMOS SDO LVCMOS O INT ...

Page 12

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 1.0 FUNCTIONAL DESCRIPTION The XRT91L34 Quad Channel CDR is designed to operate with a multichannel SONET Framer/ASIC device and provide a high-speed serial clock and data recovery interface to optical networks. ...

Page 13

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 1.3 Reference Clock Input The XRT91L34 can accept either a 19.44 MHz or 77.76 MHz Differential clock input at REFCLKP Single-Ended LVTTL clock input at TTLREFCLK. The REFCLKP/N ...

Page 14

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 2.0 RECEIVE SECTION The receive section of XRT91L34 includes four differential input buffers RXDI[3:0]P/N, followed by clock and data recovery units (CDR) and recovered serial data and clock differential output drivers. ...

Page 15

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 The receive serial inputs can also be AC coupled to an optical module or an electrical interface. A simplified Differential LVPECL AC coupling using external passive components block diagram is ...

Page 16

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR ABLE N AME REF Reference clock duty cycle DUTY REF Reference clock frequency tolerance TOL TOL Input jitter tolerance with 1 MHz < f < 20 MHz PRBS ...

Page 17

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 2.4 Internal Digital Loss of Signal and External Signal Detection XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection (SDEXT) for detecting and determining ...

Page 18

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 2.5 Multichannel Recovered Output Interface The recovered data RXDO[3:0]P/N differential output drivers along with the recovered clock RXCLKO[3:0]P/N differential output drivers can be configured for LVDS or Differential LVPECL standard operation. ...

Page 19

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 2.6 Differential Recovered Data Output Timing The differential recovered data and clock outputs operating at the STS-12/STM-4 or STS-3/STM-1 or STS-1/ STM-0 datarates will adhere to the data valid output ...

Page 20

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 3.0 JITTER PERFORMANCE 3.1 SONET Jitter Requirements SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of each of these types of jitter are given below. ...

Page 21

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 F 12. XRT91L34 M IGURE 100.00 10.00 1.00 0.10 0.01 1E+0 F 13. XRT91L34 M IGURE Jitte r T ole rance , G R -253 -12 (622 M ...

Page 22

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 3.1.2 Rx Jitter Transfer Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. It displays the ability ...

Page 23

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 F 16. XRT91L34 M IGURE Jitte r T ransfe r, G R253H , O C -12 (622 M bps -10 -15 -20 -25 -30 1E+1 XRT91L34 J ...

Page 24

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The Serial Microprocessor Interface uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the device. Optional pins such as SDO, INT, and ...

Page 25

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 4.2 16 ERIAL ATA NPUT ESCRITPTION The serial data input is sampled on the rising edge of SCLK. For read operations, the SDO signal is ...

Page 26

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 5.0 REGISTER MAP AND BIT DESCRIPTIONS The XRT91L34 consists of 6 Common Registers including the Device ID and Revision ID registers and 12 channelized registers. Table 8 below presents the overall ...

Page 27

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 COMMON CONTROL REGISTERS ABLE ICROPROCESSOR AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved ...

Page 28

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR T 10: M ABLE ICROPROCESSOR AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit ...

Page 29

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 T 12: M ABLE ICROPROCESSOR AME D7 Device "ID" The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the revision "ID", the device "ID" is ...

Page 30

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR CHANNELIZED REGISTERS T 15: M ABLE ICROPROCESSOR C C HANNEL ONTROL AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used ...

Page 31

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 T 16: M ABLE ICROPROCESSOR ONFIGURATION AND NTERRUPT NABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is ...

Page 32

XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR T 17: M ABLE ICROPROCESSOR NTERRUPT TATUS ONTROL AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used ...

Page 33

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 6.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Air Thermal Resistance of LQFP Package..... Case Thermal Resistance of LQFP Package. ESD Protection (HBM)..........................................>2000V T 18: A ABLE BSOLUTE S T YMBOL YPE ...

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