89H24NT24G2ZBHLI IDT, 89H24NT24G2ZBHLI Datasheet - Page 3

• Manufacturer Part Number: 89H24NT24G2ZBHLI
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H24NT24G2ZBHLI

• Part # Aliases: IDT89H24NT24G2ZBHLI

Block Diagram
Multiplexer / Demultiplexer
NTB ports
Mapping table
entries
Mapping windows
Address translation Direct-address and
Doorbell registers
Message registers
Transaction Layer
Function
Data Link Layer
SerDes
(Port 0)
Logical
Layer
Phy
x1
(Ports 0 through 7 are not capable of merging with an adjacent port)
Up to 8
Up to 64 for entire
device
Six 32-bits or three
64-bits
lookup table trans-
lations
32 bits
4 inbound and out-
bound registers of
32-bits
Frame Buffer
Number
24-Port Switch Core / 24 Gen2 PCI Express Lanes
Table 1 Non-Transparent Bridge Function Summary
Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Each device can have up to 64 masters ID for address and ID translations.
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets
a corresponding bit at the inbound doorbell in the other domain.
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Figure 1 PES24NT24G2 Block Diagram
Route Table
3 of 35
Arbitration
Port
Description
Scheduler
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Port 23
SerDes
Logical
Layer
Phy
x1
April 16, 2013