25LC020A-I/SN Microchip Technology, 25LC020A-I/SN Datasheet - Page 12
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25LC020A-I/SN
Manufacturer Part Number
25LC020A-I/SN
Description
IC EEPROM 2KBIT 10MHZ 8SOIC
Manufacturer
Microchip Technology
Specifications of 25LC020A-I/SN
Memory Size
2K (256 x 8)
Package / Case
8-SOIC (3.9mm Width)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Organization
256 K x 8
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Access Time
50 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
25LC020A-I/SN
Manufacturer:
MCP
Quantity:
3 800
Company:
Part Number:
25LC020A-I/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
25LC020A-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
25AA020A/25LC020A
2.7
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
• After a byte write, page write or STATUS register
• CS must be set high after the proper number of
• Access to the array during an internal write cycle
TABLE 2-4:
DS21833D-page 12
x = don’t care
the write enable latch
write, the write enable latch is reset
clock cycles to start an internal write cycle
is ignored and programming is continued
1 (high)
1 (high)
0 (low)
(pin 3)
WP
Data Protection
WRITE-PROTECT FUNCTIONALITY MATRIX
(SR bit 1)
WEL
x
0
1
Protected Blocks
Protected
Protected
Protected
Preliminary
2.8
The 25XX020A powers on in the following state:
• The device is in low-power Standby mode
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
(CS = 1)
enter active state
Unprotected Blocks
Power-On State
Protected
Protected
Writable
© 2007 Microchip Technology Inc.
STATUS Register
Protected
Protected
Writable