25LC320/SN Microchip Technology, 25LC320/SN Datasheet - Page 11

• Manufacturer Part Number: 25LC320/SN
• Description: IC EEPROM 32KBIT 2MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25LC320/SN

• Memory Size: 32K (4K x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: 0°C ~ 70°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 4 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 2 MHz
• Access Time: 230 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.6
The Write Status Register instruction (WRSR) allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two,
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
FIGURE 3-7:
 2004 Microchip Technology Inc.
SCK
SO
CS
SI
Write Status Register Instruction
(WRSR)
0
0
WRITE STATUS REGISTER TIMING SEQUENCE
0
1
0
2
instruction
0
3
0
4
0
5
25AA320/25LC320/25C320
High-impedance
0
6
1
7
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-7 for the WRSR timing sequence.
TABLE 3-2:
7
8
BP1
6
0
0
1
1
9
data to Status register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
13
2
Array Addresses
Write-Protected
(0C00h - 0FFFh)
(0800h - 0FFFh)
(0000h - 0FFFh)
14
1
upper 1/4
upper 1/2
DS21227E-page 11
none
all
15
0