AT28BV64B-20JU Atmel, AT28BV64B-20JU Datasheet - Page 4

IC EEPROM 64KBIT 200NS 32PLCC

AT28BV64B-20JU

Manufacturer Part Number
AT28BV64B-20JU
Description
IC EEPROM 64KBIT 200NS 32PLCC
Manufacturer
Atmel
Datasheet

Specifications of AT28BV64B-20JU

Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
200ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-PLCC
Organization
8 K x 8
Interface Type
SPI
Access Time
150 ns
Output Enable Access Time
80 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT28BV64B-20JU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT28BV64B-20JU
Manufacturer:
ATMEL
Quantity:
9 626
4.4
4.5
4.6
4.6.1
4.6.2
4.7
4
DATA Polling
Toggle Bit
Data Protection
Device Identification
AT28BV64B
Hardware Protection
Software Data Protection
The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is valid
on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the
write cycle.
In addition to DATA Polling, the AT28BV64B provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28BV64B in the following ways:
(a) V
out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high
or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
A software-controlled data protection feature has been implemented on the AT28BV64B. Soft-
ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV64B can only be written using the software data protection feature. A series of three
write commands to specific addresses with specific data must be presented to the device before
writing in the byte or page mode. The same three write commands must begin each write opera-
tion. All software write commands must obey the page mode write timing specifications. The
data in the 3-byte command sequence is not written to the device; the addresses in the com-
mand sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write timers.
No data will be written to the device; however, for the duration of t
tively be polling operations.
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH, the additional bytes may be
written to or read from in the same manner as the regular memory array.
CC
power-on delay – once V
®
has incorporated both hardware and software features that will protect the
CC
has reached 1.8V (typical) the device will automatically time
WC
, read operations will effec-
0299I–PEEPR–4/09

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