AS7C1026B-12JCN Alliance Memory, AS7C1026B-12JCN Datasheet - Page 2

• Manufacturer Part Number: AS7C1026B-12JCN
• Description: SRAM 1M, 5V, 12ns FAST 64K x 16 Asynch SRAM
• Manufacturer: Alliance Memory

Specifications of AS7C1026B-12JCN

• Rohs: yes
• Memory Size: 1 Mbit
• Organization: 64 K x 16
• Access Time: 12 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: SOJ-32
• Interface: Parallel
• Maximum Clock Frequency: 83 MHz
• Factory Pack Quantity: 16

Truth table
Functional description
The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words ×
16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
high-performance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I
standby power is reached (I
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry
standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key:
3/26/04, v 1.3
CE
H
L
L
L
L
L
L
L
L
H = high, L = low, X = don’t care.
Absolute maximum ratings
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC
applied
DC current into outputs (low)
WE
X
H
H
H
H
X
L
L
L
CC
Parameter
relative to GND
SB1
). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
OE
X
X
X
X
H
X
L
L
L
AA
, t
LB
RC
X
H
H
X
H
L
L
L
L
, t
WC
Alliance Semiconductor
) of 10/12/15/20 ns with output enable access times (t
Symbol
UB
I
T
X
H
H
X
H
T
L
L
L
L
V
V
OUT
P
bias
stg
D
t1
t2
I/O0–I/O7
High Z
High Z
High Z
High Z
D
D
D
D
OUT
OUT
IN
IN
®
–0.50
–0.50
Min
–65
–55
–
–
I/O8–I/O15
High Z
High Z
High Z
High Z
D
D
D
D
OUT
OUT
IN
IN
V
CC
+150
+125
Max
+7.0
1.0
20
SB
+0.50
power. If the bus is static, then full
OE
Write I/O0–I/O15 (I
Write I/O8–I/O15 (I
Read I/O0–I/O15 (I
Read I/O8–I/O15 (I
Write I/O0–I/O7 (I
Read I/O0–I/O7 (I
Output disable (I
Standby (I
) of 5, 6, 7, 8 ns are ideal for
Mode
AS7C1026B
Unit
mA
°C
°C
W
SB
V
V
), I
P. 2 of 10
SBI
CC
CC
CC
CC)
CC
CC
CC
)
)
)
)
)
)
)