7130SA55J IDT, 7130SA55J Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
7130SA55J
Manufacturer Part Number
7130SA55J
Description
SRAM
Manufacturer
IDT
Datasheet
1.7130LA55PDGI.pdf
(21 pages)
Specifications of 7130SA55J
Part # Aliases
IDT7130SA55J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
7130SA55J
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
7130SA55JI
Manufacturer:
IDT
Quantity:
184
Part Number:
7130SA55JI
Manufacturer:
IDT
Quantity:
20 000
DATA
Timing Waveform of Write with Port-to-Port Read and BUSY
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
DATA
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
ADDR
BUSY
WH
ADDR
OUT"B"
R/ W
L
must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
= CE
IN"A"
"B"
"B"
"A "
IL
"A"
for the reading port.
R
= V
IL
BUSY
R/W
R/W
"B"
"B"
"A"
t
APS
(1)
"B"
, until BUSY
BDD
is ignored for slave (IDT7140).
"B"
t
goes HIGH.
BAA
t
WB
MATCH
t
WC
15
(2)
t
WP
(3)
t
WP
Military, Industrial and Commercial Temperature Ranges
MATCH
t
VALID
DW
t
BDA
t
WDD
t
WH
(1)
t
DDD
2689 drw 13
t
DH
t
BDD
(2,3,4)
,
VALID
2689 drw 12