7008L20JI IDT, 7008L20JI Datasheet - Page 13

• Manufacturer Part Number: 7008L20JI
• Description: SRAM
• Manufacturer: IDT
• Type: Dual Port Static RAMr

Specifications of 7008L20JI

• Memory Size: 512 kbit
• Organization: 64 k x 8
• Access Time: 20 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 50 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-84
• Interface: TTL
• Memory Type: Asynchronous
• Part # Aliases: IDT7008L20JI

Timing Waveform of Write with Port-to-Port Read and BUSY
DATA
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = V
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
DATA
ADDR
ADDR
WH
WB
BUSY
L
R/W
OUT "B"
is only for the 'Slave' version.
must be met for both BUSY input (SLAVE) and output (MASTER).
= CE
IN "A"
IL
"A"
"A"
"B"
"B"
for the reading port.
R
IL
= V
(SLAVE), then BUSY is an input (BUSY
IL,
refer to Chip Enable Truth Table.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
APS
"A"
is ignored for M/S = V
= V
IH
"B"
t
and BUSY
WB
goes HIGH.
(3)
"B"
MATCH
= "don't care", for this example).
IL
t
6.42
WC
(SLAVE).
t
13
WP
(2)
t
Military, Industrial and Commercial Temperature Ranges
WP
MATCH
IL
t
DW
t
WDD
)
VALID
t
WH
(1)
3198 drw 14
t
DDD
(3)
(2,5)
t
BDA
(M/S = V
t
DH
3198 drw 13
t
BDD
IH
VALID
)
(4)