CAT1641WI-28-G ON Semiconductor, CAT1641WI-28-G Datasheet - Page 10

• Manufacturer Part Number: CAT1641WI-28-G
• Description: Supervisory Circuits CPU w/64K
• Manufacturer: ON Semiconductor

Specifications of CAT1641WI-28-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.85 V
• Overvoltage Threshold: 3 V
• Output Type: Active High, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 3 V

Byte Write
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address bytes that are to be written into the address pointers
of the device. After receiving another acknowledge from the
Page Write
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to
additional 63 bytes. After each byte has been transmitted, the
CAT1640/41 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
In the Byte Write mode, the Master device sends the
The CAT1640/41 writes up to 64 bytes of data in a single
FROM TRANSMITTER
FROM RECEIVER
SD
SCL
DATA OUTPUT
DATA OUTPUT
A
Default Configuration
SCL FROM
MASTER
START BIT
STA
RT
Figure 6. Acknowledge Timing
Figure 7. Slave Address Bits
Figure 5. Start/Stop Timing
WRITE OPERATIONS
1
http://onsemi.com
1
0
10
1
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1640/41
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1640/41 in a single write cycle.
If the Master transmits more than 64 bytes before sending
When all 64 bytes are received, and the STOP condition
0
A2
A1
8
STOP BIT
A0
ACKNOWLEDGE
R/W
9