MAX6848KAZD7-T Maxim Integrated, MAX6848KAZD7-T Datasheet - Page 7

• Manufacturer Part Number: MAX6848KAZD7-T
• Description: Battery Management
• Manufacturer: Maxim Integrated
• Series: MAX6846, MAX6847, MAX6848, MAX6849r

Specifications of MAX6848KAZD7-T

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: SOT-23

The low-battery outputs are available in active-low
(LBO, LBOL, LBOH), open-drain configurations. The
low-battery outputs can be pulled to a voltage indepen-
dent of V
to monitor and operate from direct battery voltage while
interfacing to higher voltage microprocessors.
The MAX6846/MAX6847 single-output voltage monitors
provide a single low-battery output, LBO. LBO asserts
when LTHIN drops below V
for at least 150ms after HTHIN rises above V
Figure 2). The MAX6848/MAX6849 dual-output voltage
monitors provide two low-battery outputs: LBOH and
LBOL. LBOH asserts when HTHIN drops below V
and remains asserted for at least 150ms after HTHIN
Figure 1a. MAX6847 Functional Diagram
HTHIN
LTHIN
V
V
CC
DD
Low-Power, Adjustable Battery Monitors with
CC
1.23V
or V
DETECT
DD
DETECT
DETECT
615mV
HTH
LTH
V
_______________________________________________________________________________________
TH
, up to 5.5V. This allows the device
LBO TIMEOUT
TIMEOUT
PERIOD
RESET
PERIOD
LTH
Hysteresis and Integrated µP Reset
Low-Battery Output
MR
and remains asserted
R
S
MAX6847
V
CC
Q
Q
V
HTH
CC
HTH-
(see
LBO
RESET
rises above V
below V
after LTHIN rises above V
rising V
plete before the LBOH timeout period begins.
The MAX6846–MAX6849 provide an active-low reset
output (RESET). RESET is asserted when the voltage at
V
asserted for the reset timeout period after V
the threshold. If V
before the reset timeout period is completed, the inter-
nal timer restarts (see Figure 4). The MAX6846/
MAX6848 have open-drain reset outputs, while the
MAX6847/MAX6849 have push-pull reset outputs.
Figure 1b. MAX6848 Functional Diagram
HTHIN
LTHIN
CC
V
V
DD
CC
falls below the reset threshold level. Reset remains
DD
LTH-
615mV
input, the LBOL timeout period must com-
1.23V
and remains asserted for at least 150ms
HTH+
HYST
HYST
5%
5%
CC
. LBOL asserts when LTHIN drops
DETECT
DETECT
DETECT
HTH
LTH
V
goes below the reset threshold
TH
LTH+
(see Figure 3). For fast-
MAX6848
TIMEOUT
PERIOD
RESET
TIMEOUT
PERIOD
LBO
Reset Output
CC
exceeds
LBOL
LBOH
RESET
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