71V016SA12BFG IDT, 71V016SA12BFG Datasheet - Page 7

• Manufacturer Part Number: 71V016SA12BFG
• Description: SRAM
• Manufacturer: IDT

Specifications of 71V016SA12BFG

• Product Category: SRAM
• Rohs: yes
• Part # Aliases: IDT71V016SA12BFG

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
DATA
ADDRESS
ADDRESS
DATA
on the bus for the required t
BHE, BLE
BHE, BLE
DATA
DATA
OUT
OUT
WE
WE
CS
CS
IN
IN
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t
t
AS
t
AS
t
t
AW
AW
t
WP
CW
t
t
must be greater than or equal to t
WP
WP
(2)
t
t
t
WC
BW
WC
6.42
7
t
CW
(2)
t
BW
DATA
t
DATA
t
DW
DW
IN
IN
Commercial and Industrial Temperature Ranges
VALID
VALID
WHZ
+ t
DW
t
t
DH
DH
t
WR
t
to allow the I/O drivers to turn off and data to be placed
WR
(1,4)
3834 drw 09
3834 drw 10
(1,4)
WP
.