70V3319S133BF IDT, 70V3319S133BF Datasheet - Page 18

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70V3319S133BF

Manufacturer Part Number
70V3319S133BF
Description
SRAM 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
Manufacturer
IDT
Datasheet

Specifications of 70V3319S133BF

Part # Aliases
IDT70V3319S133BF
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)
Timing Waveform of Counter Repeat
NOTES:
1. CE
2. CE
3. The "Internal Address" is equal to the "External Address" when ADS = V
4. Addresses do not have to be accessed sequentially since ADS = V
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
7. CNTEN = V
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
use only.
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
written to during this cycle.
0
0
, UB, LB, and R/W = V
, UB, LB = V
INTERNAL
ADDRESS
ADDRESS
INTERNAL
ADDRESS
ADDRESS
DATA
REPEAT
DATA
DATA
CNTEN
CNTEN
IL
CLK
ADS
CLK
ADS
R/
advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
OUT
IN
W
IN
IL
(3)
(3)
; CE
(5)
1
= V
t
Ax
SRPT
IL
t
t
IH
t
SA
SAD
; CE
SD
.
An
Dn
EXTERNAL
ADDRESS
t
HRPT
1
t
t
WRITE
t
HAD
HD
t
HA
CH2
and REPEAT = V
t
EXECUTE
CH2
REPEAT
t
CYC2
t
CYC2
An
t
CL2
t
t
t
CL2
(7)
SCN
t
t
SAD
(6)
t
SD
SW
SCN
Dn + 1
D
t
0
t
HCN
t
HAD
t
t
WITH COUNTER
HW
HD
LAST ADS LOAD
HCN
IH
LAST ADS
ADDRESS
.
WRITE
WRITE
Dn + 1
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference
An + 1
COUNTER HOLD
IL
(1)
LAST ADS
ADDRESS
and equals the counter output when ADS = V
READ
6.42
WRITE
18
(2)
Dn + 2
ADDRESS + 1
LAST ADS +1
LAST ADS
READ
An + 2
Industrial and Commercial Temperature Ranges
t
SA
Q
Dn + 3
An
LAST
WRITE WITH COUNTER
t
HA
ADDRESS n
READ
An
An + 3
IH
.
(4)
An + 1
Q
LAST+1
Dn + 4
ADDRESS n+1
READ
An + 1
An + 4
5623 drw 18
5623 drw 19
An + 2
Qn

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