7024S55JI8 IDT, 7024S55JI8 Datasheet - Page 16

• Manufacturer Part Number: 7024S55JI8
• Description: SRAM
• Manufacturer: IDT

Specifications of 7024S55JI8

• Part # Aliases: IDT7024S55JI8

Waveform of Interrupt Timing
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
4. INT
ADDR
ADDR
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
R/W
INT
R/W
OE
INT
CE
CE
X
X
X
L
R
L
"B"
"B"
"B"
"B"
"A"
"A"
"A"
"B"
and
L
R
= V
INT
= V
CE
L
IL
IL
L
X
X
L
, then no change.
, then no change.
must be initialized at power-up.
L
L
= BUSY
Left Port
OE
R
X
X
X
L
= V
L
IH
.
A
t
11L
AS
FFF
FFE
t
AS
X
X
-A
(3)
t
0L
(3)
INR
t
INS
(3)
(3)
INTERRUPT CLEAR ADDRESS
INT
INTERRUPT SET ADDRESS
X
X
H
L
(3)
(2)
L
(1)
R/W
(1,4)
X
X
X
L
R
t
RC
t
WC
6.42
16
CE
X
X
L
L
R
Military, Industrial and Commercial Temperature Ranges
Right Port
(2)
OE
X
X
X
L
(2)
R
t
WR
A
(4)
11R
FFF
FFE
X
X
-A
0R
INT
H
X
X
L
(2)
(3)
R
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Function
L
R
Flag
L
Flag
R
Flag
Flag
2740 drw 17
2740 drw 18
2740 tbl 16