IS61NLF102418-7.5TQLI-TR ISSI, IS61NLF102418-7.5TQLI-TR Datasheet
IS61NLF102418-7.5TQLI-TR
Specifications of IS61NLF102418-7.5TQLI-TR
Related parts for IS61NLF102418-7.5TQLI-TR
IS61NLF102418-7.5TQLI-TR Summary of contents
Page 1
... IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • ...
Page 2
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 BLOCK DIAGRAM x 72: A [0:17 36: A [0:18] or ADDRESS x 18: A [0:19] REGISTER CLK CONTROL LOGIC K CKE CE CE2 CE2 CONTROL } ADV REGISTER WE BWŸ X (X=a-h, a- DQx/DQPx 2 A2-A17 or A2-A18 or A2-A19 MODE BURST ADDRESS A0-A1 A'0-A'1 COUNTER WRITE WRITE ADDRESS ADDRESS REGISTER ...
Page 3
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 Bottom View 209-Ball BGA Integrated Silicon Solution, Inc. — www.issi.com — Rev. D 04/11/12 Bottom View 165-Ball 15mm BGA 1-800-379-4774 3 ...
Page 4
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 PIN CONFIGURATION — 256K x 72, 209-Ball PBGA (TOP VIEW DQg DQg A B DQg DQg BWc C DQg DQg BWh D DQg DQg DQPg DQPc V ddq F DQc DQc DQc DQc ...
Page 5
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 PIN CONFIGURATION — 512K CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq G DQc DQc V ddq H NC VDD NC J DQd DQd V ddq K DQd ...
Page 6
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 165-PIN PBGA PACKAGE CONFIGURATION 1024K x 18 (TOP VIEW) CE2 DDQ DQb DDQ V DQb E NC DDQ DQb DDQ ...
Page 7
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 PIN CONFIGURATION 100-Pin TQFP 100 DQPc 2 DQc 3 DQc 4 V DDQ 5 Vss 6 DQc 7 DQc 8 DQc 9 DQc 10 Vss 11 V DDQ 12 DQc 13 DQc Vss ...
Page 8
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 STATE DIAGRAM BEGIN READ READ READ BURST BURST BURST READ SYNCHRONOUS TRUTH TABLE Address Operation Used Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read External Address Continue Burst Read Next Address NOP/Dummy Read External Address Dummy Read Next Address Begin Burst Write External Address Continue Burst Write ...
Page 9
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H Read L L Write L Deselected L Notes means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation WE READ H WRITE BYTE a L WRITE BYTE b L WRITE ALL BYTEs ...
Page 10
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 WRITE TRUTH TABLE (x72) Operation WE READ H WRITE BYTE a L WRITE BYTE b L WRITE BYTE c L WRITE BYTE d L WRITE BYTE e L WRITE BYTE f L WRITE BYTE g L WRITE BYTE h L WRITE ALL BYTEs L WRITE ABORT/NOP L Notes means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE ...
Page 11
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 LINEAR BURST ADDRESS TABLE A1', A0' = 1,1 ABSOLUTE MAxIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation d I Output Current (per I/O) ouT Voltage Relative ouT V Voltage Relative for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
Page 12
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 OPERATING RANGE (IS61NLFx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C OPERATING RANGE (IS61NVFx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C DC ...
Page 13
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 CAPACITANCE (1,2) Symbol Parameter c Input Capacitance In c Input/Output Capacitance ouT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT Zo= 50Ω ...
Page 14
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 14 Unit 0V to 2.5V 1.5 ns 1.25V OUTPUT 50Ω 1.25V Integrated Silicon Solution, Inc. — www.issi.com — ...
Page 15
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t (2,3) Clock High to Output Low-Z kqlZ t Clock High to Output High-Z (2,3) kqhZ t Output Enable to Output Valid oeq t Output Enable to Output Low-Z ...
Page 16
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SLEEP MODE ZZ active to input ignored PdS t ZZ inactive to input sampled PuS t ZZ active to SLEEP current ZZI t ZZ inactive to exit SLEEP current rZZI SLEEP MODE TIMING CLK t PDS ZZ setup cycle ZZ t ZZI Isupply I All Inputs ...
Page 17
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 READ CYCLE TIMING CLK t t ADVS ADVH ADV Address WRITE t SE CKE t t CES CEH OEQ OEHZ t OEHZ Data Out Q1-1 NOTES: WRITE = L means and BWx = and BWX = L ...
Page 18
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 WRITE CYCLE TIMING t KH CLK t ADV Address A1 A2 WRITE CKE CE OE Data In D1-1 t OEHZ Data Out Q0-4 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...
Page 19
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 SINGLE READ/WRITE CYCLE TIMING CLK CKE Address WRITE CE ADV OE t OEQ t OELZ Data Out Data In D2 NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...
Page 20
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 CKE OPERATION TIMING CLK CKE Address A1 WRITE CE ADV KQLZ Data Out Q1 Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...
Page 21
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 CE OPERATION TIMING CLK CKE A1 A2 Address WRITE CE ADV OE t OEQ t OELZ Q1 Q2 Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...
Page 22
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61NLFX and IS61NVFX have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices us- ing 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. ...
Page 23
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (V rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation ...
Page 24
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buf- fers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed ...
Page 25
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 INSTRUCTION CODES Code Instruction 000 EXTEST 001 IDCODE 010 SAMPLE-Z 011 RESERVED 100 SAMPLE/PRELOAD 101 RESERVED 110 RESERVED 111 BYPASS TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 0 Integrated Silicon Solution, Inc. — www.issi.com — ...
Page 26
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage oh1 V Output HIGH Voltage oh2 V Output LOW Voltage ol1 V Output LOW Voltage ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Leakage Current x Notes: 1. All Voltage referenced to Ground. 2. Overshoot: V (AC) ≤ V +1.5V for ≤ ≤ Undershoot: V (AC) 0.5V for t Il ...
Page 27
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMING 1 t THTH TCK t MVTH TMS t DVTH TDI TDO Integrated Silicon Solution, Inc. — www.issi.com — Rev. D 04/11/12 TAP Output Load Equivalent 1ns 1 ...
Page 28
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 209 BOUNDARY SCAN ORDER (256K x 72) 28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/11/12 ...
Page 29
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 165 PBGA BOUNDARY SCAN ORDER (x 36) Signal Bump B it # Name ID Bit # 1 MODE 11P ...
Page 30
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 165 PBGA BOUNDARY SCAN ORDER (x 18) Signal Bump B it # Name ID Bit # 1 MODE 11P ...
Page 31
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Access Time 6.5 7.5 6.5 7.5 Industrial Range: -40°C to +85°C Access Time 6.5 7.5 6.5 7.5 ...
Page 32
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Access Time 6.5 7.5 6.5 7.5 Industrial Range: -40°C to +85°C Access Time 6.5 7.5 6.5 7.5 ...
Page 33
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 Integrated Silicon Solution, Inc. — www.issi.com — Rev. D 04/11/12 1-800-379-4774 33 ...
Page 34
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 34 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/11/12 ...
Page 35
... IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 Integrated Silicon Solution, Inc. — www.issi.com — Rev. D 04/11/12 1-800-379-4774 35 ...