STM8S003K3T6C STMicroelectronics, STM8S003K3T6C Datasheet - Page 11

• Manufacturer Part Number: STM8S003K3T6C
• Description: 8-bit Microcontrollers - MCU 8-bit MCU Value Line 16 MHz 8kb FL 128EE
• Manufacturer: STMicroelectronics

Specifications of STM8S003K3T6C

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: STM8
• Data Bus Width: 8 bit

STM8S003K3 STM8S003F3
4.3
4.4
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
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Interrupt controller
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Flash program memory and data EEPROM
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Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
the data EEPROM, and the option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to modify the content
of the main program memory and data EEPROM, or to reprogram the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
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The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 27 external interrupts on 6 vectors including TLI
Trap and reset interrupts
8 Kbytes of Flash program single voltage Flash memory
128 bytes of true data EEPROM
User option byte area
Main program memory: 8 Kbytes minus UBC
User-specific boot code (UBC): Configurable up to 8 Kbytes
DocID018576 Rev 3
Product overview
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