M93C66-WMN6TP STMicroelectronics, M93C66-WMN6TP Datasheet - Page 18
![IC EEPROM 4KBIT 2MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M93C66-WMN6TP
Manufacturer Part Number
M93C66-WMN6TP
Description
IC EEPROM 4KBIT 2MHZ 8SOIC
Manufacturer
STMicroelectronics
Specifications of M93C66-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
4K (512 x 8 or 256 x 16)
Speed
2MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Organization
512 x 8
Interface Type
Microwire
Maximum Clock Frequency
2 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8660-2
M93C66-WMN6TP
M93C66-WMN6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M93C66-WMN6TP
Manufacturer:
ST
Quantity:
50 000
Part Number:
M93C66-WMN6TP
Manufacturer:
ST
Quantity:
20 000
READY/BUSY status
6
7
8
18/37
READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
Common I/O operation
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a
current limiting resistor, to form a common, single-wire data bus. Some precautions must be
taken when operating the memory in this way, mostly to prevent a short circuit current from
flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output
(Q). Please see the application note AN394 for details.
Doc ID 4997 Rev 10
M93C86, M93C76, M93C66, M93C56, M93C46
SLSH
, before this status information