M24C01-WBN6P STMicroelectronics, M24C01-WBN6P Datasheet - Page 14

• Manufacturer Part Number: M24C01-WBN6P
• Description: IC EEPROM 1KBIT 400KHZ 8DIP
• Manufacturer: STMicroelectronics

Specifications of M24C01-WBN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 128 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Configuration: 128 X 8
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8557; M24C01-WBN6P

Device operation
3.6.2
14/39
the addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in
Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write
Control (WC) being driven High (during the period from the Start condition until the end of
the address byte), the device replies to the data bytes with NoAck, as shown in
and the locations are not modified. After each byte is transferred, the internal byte address
counter (the 4 least significant address bits only) is incremented. The transfer is terminated
by the bus master generating a Stop condition.
Figure 8.
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
Write mode sequences with WC = 0 (data write enabled)
Dev Select
Dev Select
ACK
Doc ID 5067 Rev 16
Data in N
R/W
R/W
ACK
ACK
Byte address
Byte address
ACK
M24C16, M24C08, M24C04, M24C02, M24C01
ACK
ACK
Data in 1
Data in
ACK
ACK
Data in 2
Figure
ACK
8.
Data in 3
Figure
AI02804c
7,