M93C66-WMN6P STMicroelectronics, M93C66-WMN6P Datasheet - Page 19

• Manufacturer Part Number: M93C66-WMN6P
• Description: IC EEPROM 4KBIT 2MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M93C66-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 512 x 8
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Configuration: 512 X 8, 256 X 16
• Clock Frequency: 2MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5672-5

M93C86, M93C76, M93C66, M93C56, M93C46
9
Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the master (the microcontroller). This can lead to a
misalignment of the instruction of one or more bits (as shown in
the writing of erroneous data at an erroneous address.
To combat this problem, the M93Cx6 has an on-chip counter that counts the clock pulses
from the start bit until the falling edge of the Chip Select Input (S). If the number of clock
pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL
instruction is aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the
M93Cx6 family, are summarized in
Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the
x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is:
Figure 7.
S
D
C
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
START
Write sequence with one clock glitch
"0"
WRITE
Doc ID 4997 Rev 11
"1"
Table 5.
An
to
Glitch
Table
An-1
ARE SHIFTED BY ONE BIT
ADDRESS AND DATA
7.. For example, a Write Data to
An-2
Figure
Clock pulse counter
7.) and may lead to
D0
AI01395
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