M95256-RMN6TP STMicroelectronics, M95256-RMN6TP Datasheet
M95256-RMN6TP
Specifications of M95256-RMN6TP
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M95256-RMN6TP Summary of contents
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... Enhanced ESD Protection ■ Packages ® – ECOPACK2 (RoHS compliant and Halogen-free) March 2011 M95256 M95256-W M95256-R 256 Kbit serial SPI bus EEPROM with high-speed clock UFDFPN8 (MB, MC) Doc ID 12276 Rev 13 M95256-DR SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width 2 × ...
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... Write Status Register (WRSR 5.5 Read from Memory Array (READ 5.6 Write to Memory Array (WRITE 2/47 M95256-DR, M95256, M95256-W, M95256 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Doc ID 12276 Rev 13 ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.6.1 5.7 Read Identification Page (available only in M95256-DR devices 5.8 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9 Read Lock Status (available only in M95256-DR devices 5.10 Lock ID (available only in M95256-DR devices Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... DC characteristics (M95256-W, device grade Table 16. DC characteristics (M95256-R, M95256-DR, device grade Table 17. AC characteristics (M95256, device grade Table 18. AC characteristics, M95256-W, device grade Table 19. AC characteristics (M95256-W, device grade Table 20. AC characteristics (M95256-DR, M95256-R device grade 6 Table 21. SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 38 Table 22. TSSOP8 – ...
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... SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 38 Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 12276 Rev 13 List of figures 5/47 ...
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... They are accessed by a high speed SPI- compatible bus. Their memory array is organized as 32768 × 8 bits. The M95256-DR also offers an additional page, named the Identification Page (64 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 3. WLCSP connections (top view, marking side, with balls on the underside) Caution: As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light. ...
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... Memory organization The memory is organized as shown in Figure 4. Block diagram HOLD W Control Logic Address Register and Counter 8/47 M95256-DR, M95256, M95256-W, M95256-R Figure 4. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder Doc ID 12276 Rev 13 Status Register Size of the Read only ...
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... M95256-DR, M95256, M95256-W, M95256-R 3 Signal description See Figure 1: Logic diagram connected to this device. 3.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written ...
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... POR threshold, the device is reset and enters the Standby CC Power mode, however, the device must not be accessed until V stable V voltage within the specified [V CC and Table 10). 10/47 M95256-DR, M95256, M95256-W, M95256-R supply voltage range must be applied (see CC(min) CC(max) 10). ...
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... M95256-DR, M95256, M95256-W, M95256-R 3.8.2 Power-up conditions When the power supply is turned on, V time, the Chip Select (S) line is not allowed to float but should follow the V therefore recommended to connect the S line to V Figure 17). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S) ...
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... For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). 12/47 M95256-DR, M95256, M95256-W, M95256-R Hold Condition (RDSR). Doc ID 12276 Rev 13 ...
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... M95256-DR, M95256, M95256-W, M95256-R Two points need to be noted in the previous sentence: ● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). ...
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... Read Lock Status Lock ID 1. Address bit A10 must be 0, all other address bits are Don't Care. 2. Address bit A10 must be 1, all other address bits are Don't Care. 14/47 M95256-DR, M95256, M95256-W, M95256-R Description Write Enable Write Disable Read Status Register ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then enters a wait state ...
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... Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status Register format b7 SRWD Status Register Write Protect 16/47 M95256-DR, M95256, M95256-W, M95256-R Table 5) becomes protected against Write Doc ID 12276 Rev 13 Figure 8 ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 8. Read Status Register (RDSR) sequence High Impedance Q 5.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must have been previously executed ...
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... If Write Protect (W) input pin is permanently tied high, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. 18/47 M95256-DR, M95256, M95256-W, M95256-R Write protection of the Mode Status Register ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 9. Write Status Register (WRSR) sequence 5.5 Read from Memory Array (READ) As shown in Figure low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data output (Q) ...
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... Block Protect (BP1 and BP0) bits. Note: The self-timed Write cycle t events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. 20/47 M95256-DR, M95256, M95256-W, M95256 ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 11. Byte Write (WRITE) sequence The most significant address bit (b15) is Don’t Care. Figure 12. Page Write (WRITE) sequence The most significant address bit (b15) is Don’t Care Instruction 16-Bit Address High Impedance Instruction 16-Bit Address Data Byte 2 ...
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... It is therefore recommended to write data word by word (4 bytes) at address 4*N (where integer) in order to benefit from the larger amount of Write cycles. The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device in multiples of 4-byte words. 5.7 ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 13. Read Identification Page sequence 5.8 Write Identification Page The Identification Page (256 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Chip Select signal (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D) ...
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... Instructions 5.9 Read Lock Status (available only in M95256-DR devices) The Read Lock Status instruction (see locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D) ...
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... M95256-DR, M95256, M95256-W, M95256-R The instruction is not accepted, and so not executed, under the following conditions: ● if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction) ● if Status register bits (BP1,BP0) = (1,1) ● write cycle is already in progress ● ...
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... The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate. A pull-up resistor connected on each /S input (represented in slave device on the SPI bus is not selected if the bus master leaves the /S line in the high impedance state. 26/47 M95256-DR, M95256, M95256-W, M95256-R R SDO SDI SCK ...
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... M95256-DR, M95256, M95256-W, M95256-R In applications where the bus master might enter a state where all SPI bus inputs/outputs would be in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull- ...
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... Compliant with JEDEC Std J-STD-020D (for small body, Sn- assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 ) 3000 V (max) for the M95256-D and the M95256 in MLP8 package MC. ESD 28/47 M95256-DR, M95256, M95256-W, M95256-R Table 7 ...
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... Ambient operating temperature (device grade 3) A Table 9. Operating conditions (M95256-W) Symbol V Supply voltage CC Ambient operating temperature (device grade Ambient operating temperature (device grade 3) Table 10. Operating conditions (M95256-R and M95256-DR) Symbol V Supply voltage CC T Ambient operating temperature A Table 11. AC measurement conditions Symbol C Load capacitance ...
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... Figure 19. AC measurement I/O waveform Table 12. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested. Table 13. DC characteristics (M95256, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current ...
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... M95256-D and M95256 in MLP8 package MC 2. For the M95256-D and M95256 in MLP8 package MC 3. Characterized value, not tested in production µA for the M95256-D and M95256 in MLP8 package µA for the M95256-D and M95256 in MLP8 package MC Test conditions specified in Parameter Table 9 ...
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... V Output high voltage the application uses the M95256-R, M95256-DR device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 14: DC characteristics (M95256-W, device grade for the M95256-D and M95256 in MLP8 package MC 3. Only the M95256-D and M95256 in MLP8 package MC can run at 5 MHz (Preliminary data) 4. Characterized value, not tested in production µ ...
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... M95256-DR, M95256, M95256-W, M95256-R Table 17. AC characteristics (M95256, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV ...
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... DC and AC parameters Table 18. AC characteristics, M95256-W, device grade 6 Test conditions specified in Table 9 (grade 6) and Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time ...
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... M95256-DR, M95256, M95256-W, M95256-R Table 19. AC characteristics (M95256-W, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV ...
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... HOLD low to output High-Z HLQZ Write time Current products are identified by process letters “AB”. 2. New products are the M95256-D and M95256 in MLP8 package MC. For these new products, the test flow guarantees the AC parameter values defined in this table (when 2 5.0 V must never be less than the shortest possible clock period ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 20. Serial input timing S tCHSL C tDVCH D Q Figure 21. Hold timing HOLD Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tSLCH tCHDX MSB IN High Impedance tHLCH tCLHL tHLQZ tCH tCLQV Doc ID 12276 Rev 13 DC and AC parameters tSHSL ...
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... Package mechanical data 10 Package mechanical data In order to meet environmental requirements, ST offers the M95256 in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline Drawing is not to scale. Table 22. TSSOP8 – 8 lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits millimeters Typ ...
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... (2) ddd 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 40/47 M95256-DR, M95256, M95256-W, M95256-R millimeters Typ Min Max 0.550 0.450 0.600 0.020 0 0.050 0.250 ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline 1. Drawing is not to scale. Table 24. M95256-DR WLCSP, 0.5 mm pitch, package mechanical data Symbol A 0.60 A1 0.245 A2 0.355 B D 1.97 E 1.785 e 0.5 e1 0.866 e2 0.25 e3 0.433 F 0.552 G 0.392 ( Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... ST Sales Office. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 42/47 M95256-DR, M95256, M95256-W, M95256-R M95256 (1) ® (RoHs compliant) Doc ID 12276 Rev 13 – ...
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... New -V voltage range added (including the tables for DC characteristics, 2.1 AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, 2.2 and ordering information). 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 100ns 2.4 -V voltage range changed to 2.7-3.6V ...
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... W characteristics (M95256-DR, M95256-R device grade Blank option removed below Plating technology, process A modified and process V removed in Table 25: Ordering information Table 26: Available M95256x products (package, voltage range, temperature grade) added. SO8N and SO8W package specifications updated (see Package mechanical data). Package mechanical data: inches calculated from mm and rounded to 3 decimal digits ...
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... Table 20: AC characteristics (M95256-DR, M95256-R device grade 6) Updated Section 1: Description. Updated Section 5.7: Read Identification Page (available only in M95256- DR devices). 11 Updated Section 5.8: Write Identification Updated Section 5.9: Read Lock Status (available only in M95256-DR devices). Doc ID 12276 Rev 13 Revision history Changes Page. 45/47 ...
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... Section 5.6.1: ECC (error correction code) and Write cycling – Section 7: Connecting to the SPI bus – Table 7: Absolute maximum ratings Process letter K substituted with only concerned products (M95256-D and M95256 in MLP8 package MC). 13 – Rephrased “test condition” text in: Table 13: DC characteristics (M95256, device grade 3) ...
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... M95256-DR, M95256, M95256-W, M95256-R Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...