MAX802LESA+T Maxim Integrated, MAX802LESA+T Datasheet - Page 5

• Manufacturer Part Number: MAX802LESA+T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX690A, MAX692A, MAX802L, MAX802M, MAX805Lr

Specifications of MAX802LESA+T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 4.65 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Narrow
• Chip Enable Signals: No
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 500 uA
• Supply Voltage - Min: 1.2 V

The MAX3691 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, and voltage-
controlled oscillator). This device converts 4-bit-wide,
155Mbps data to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz
reference-clock signal (RCLK).
Figure 1. Functional Diagram
_______________Detailed Description
PCLKI+
PCLKI-
RCLK+
RCLK-
PD3+
PD2+
PD1+
PD0+
PD3-
PD2-
PD1-
PD0-
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
_______________________________________________________________________________________
with Clock Synthesis and LVDS Inputs
PHASE/FREQ
DETECT
PARALLEL
REGISTER
INPUT
4-BIT
FIL+ FIL-
VCO
PCLKO+ PCLKO-
The incoming parallel data is clocked into the
MAX3691 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is -0.7ns to +3.3ns. This defines a timing
window at about the PCLKO rising edge, during which
a PCLKI rising edge may occur. Figure 2 is the timing
diagram.
CONTROL
LVDS
SHIFT
LATCH
REGISTER
SHIFT
4-BIT
MAX3691
PECL
SD+
SD-
5