CY62128ELL-55SXE Cypress Semiconductor Corp, CY62128ELL-55SXE Datasheet - Page 7

• Manufacturer Part Number: CY62128ELL-55SXE
• Description: IC SRAM 1MBIT 55NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62128ELL-55SXE

• Memory Size: 1M (128K x 8)
• Package / Case: 32-SOIC (11.30mm Width)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Notes:
Document #: 38-05485 Rev. *H
16. The device is continuously selected. OE, CE
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE
19. CE is the logical combination of CE
20. The internal Write time of the memory is defined by the overlap of WE, CE = V
21. Data I/O is high impedance if OE = V
22. If CE
23. During this period, the I/Os are in output state and input signals must not be applied.
DATA OUT
CURRENT
ADDRESS
DATA OUT
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
ADDRESS
ADDRESS
SUPPLY
DATA I/O
1
V
goes HIGH or CE
CE
OE
CC
WE
OE
CE
NOTE 23
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
PREVIOUS DATA VALID
HIGH IMPEDANCE
t
PU
1
1
Figure 1. Read Cycle 1 (Address Transition Controlled)
and CE
IH
t
LZCE
transition LOW and CE
t
.
SA
Figure 3. Write Cycle No. 1 (WE Controlled)
t
HZOE
Figure 2. Read Cycle No. 2 (OE Controlled)
t
t
1
2
ACE
LZOE
. When CE
= V
t
IL
OHA
50%
t
, CE
DOE
2
1
= V
is LOW and CE
IH
t
2
AA
.
t
transition HIGH.
AW
t
t
SCE
RC
2
t
WC
is HIGH, CE is LOW; when CE
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
t
RC
RC
t
t
PWE
DATA VALID
SD
DATA VALID
[19, 20, 21, 22]
[17, 18
1
is HIGH or CE
,
19
[16, 17]
]
DATA VALID
t
t
HZOE
HA
t
HD
2
is LOW, CE is HIGH.
t
HZCE
CY62128E MoBL
t
PD
50%
IMPEDANCE
HIGH
Page 7 of 14
I
I
CC
SB
®
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