CY7C1355C-133AXC Cypress Semiconductor Corp, CY7C1355C-133AXC Datasheet - Page 12

• Manufacturer Part Number: CY7C1355C-133AXC
• Description: IC SRAM 9MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1355C-133AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 512K X 18 / 256K X 36
• Clock Frequency: 133MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1862; CY7C1355C-133AXC

Truth Table
Partial Truth Table for Read/Write
Truth Table for Read/Write
Document Number: 38-05539 Rev. *H
Deselect cycle
Deselect cycle
Deselect cycle
Continue deselect cycle
READ cycle (begin burst)
READ cycle (continue burst)
NOP/DUMMY READ (begin burst)
DUMMY READ (continue burst)
WRITE cycle (begin burst)
WRITE cycle (continue burst)
NOP/WRITE ABORT (begin burst)
WRITE ABORT (continue burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Read
Write no bytes written
Write byte A – (DQ
Write byte B – (DQ
Write byte C – (DQ
Write byte D – (DQ
Write all bytes
Read
Write - no bytes written
Write byte A – (DQ
Write byte B – (DQ
Write all bytes
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write
3. Write is defined by BW
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
selects are asserted, see Truth Table for details.
is inactive or when the device is deselected, and DQs and DQP
Operation
Function (CY7C1355C)
[2, 3, 4, 5, 6, 7, 8]
X
B
C
D
B
A
A
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
X
Function (CY7C1357C)
, and WE. See Truth Table for read/write.
B
D
A
C
A
B
)
)
)
)
)
)
[2, 3, 9]
Address
External
External
External
Current
Used
None
None
None
None
None
None
Next
Next
Next
Next
[2, 3, 9]
CE
H
X
X
X
X
L
L
X
L
X
L
X
X
X
X
1
= data when OE is active.
CE
X
H
X
H
H
X
H
X
X
X
X
L
X
X
WE
2
H
L
L
L
L
L
L
CE
X
H
X
X
X
X
X
X
X
X
L
L
L
L
3
ZZ ADV/LD WE BW
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
is valid. Appropriate write will be done based on which byte write is active.
BW
H
H
H
H
X
L
L
H
H
H
H
H
X
X
A
L
L
L
L
L
L
L
WE
H
L
L
L
L
X
X
X
X
H
X
H
X
X
X
X
X
L
L
BW
CY7C1355C, CY7C1357C
X
H
H
H
H
L
L
X
X
X
X
X
X
X
X
H
H
X
X
L
L
B
X
OE CEN CLK
BW
X
X
X
X
H
H
X
X
X
X
X
X
L
L
X
H
H
H
L
A
H
X
L
L
L
L
L
L
L
L
L
L
L
L
BW
X
H
H
H
H
L
L
C
L->H
L->H
L->H
L->H
L->H Data out (Q)
L->H Data out (Q)
L->H
L->H
L->H Data in (D)
L->H Data in (D)
L->H
L->H
L->H
X
X
= tri-state when OE
BW
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
X
H
H
H
L
BW
Page 12 of 32
DQ
B
H
H
H
H
X
L
L
–
D
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